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Exar Corporation |
FEATURES
• Superior Ruggedized 1230 Series: 2 KV ESD
• Four Quadrant Multiplication
• Stable, More Accurate Segmented DAC Approach
– 0.2 ppm/°C Linearity Tempco
– 2 ppm/°C Max Gain Error Tempco
– Lowest Sensitivity to Amplifier Offset
www.DataSheet4–U.coLmowest Output Capacitance (COUT = 80pF)
– Lower Glitch Energy
• Monotonic over Temperature Range
MP1230A/31A/32A
CMOS Microprocessor Compatible
Double-Buffered 12-Bit
Digital-to-Analog Converter
• Lower Data Bus Feedthrough @ CS = 1
• VDD from +11 V to +16 V
• Latch-Up Free CMOS Technology
• 12-Bit Bus Version: MP1208/1209/1210
• 16-Bit Upgrade: MP7636A
GENERAL DESCRIPTION
The MP1230A series are superior pin for pin replacements
for the 1230 series. The MP1230A series is manufactured using
advanced thin film resistors on a double metal CMOS process
which promotes significant improvements in reliability, latch-up
free performance and ESD protection.
The MP1230A series incorporates a unique decoding tech-
nique yielding lower glitch, higher speed and excellent accuracy
over temperature and time. 12-bit linearity is achieved without
trimming. Outstanding features include:
– Stability: integral and differential linearity tempcos are rated
at 0.2 ppm/°C typical. Monotonicity is guaranteed over all
temperature ranges. Scale factor tempco is a low 2 ppm/°C
maximum.
– Low Output Capacitance: Due to smaller MOSFET switch
geometries allowed by decoding, the output capacitance at
IOUT1 and IOUT2 is a low 80pF / 40pF and 25pF / 65 pF. This
less than half the competitive DAC 1230 series. Lower ca-
pacitance allows the MP1230A series to achieve settling
times faster than 1 µs for a 10 V step.
– Low Sensitivity to Output Amplifier Offset: The linearity er-
ror caused by amplifier offset is reduced by a factor of 2 in the
MP1230A series over conventional R-2R DACs.
The MP1230A series uses a circuit which reduces transients
in the supplies caused by DATA bus transitions at CS = 1.
SIMPLIFIED BLOCK DIAGRAM
VDD
VREF
DB11-DB4
DB3-DB0
BYTE1/BYTE2
8
INPUT LATCH DAC LATCH
DQ
DQ
8
LE
8 12
LE
VREF
RFB
IOUT1
IOUT2
CS
WR1
D
4
Q
4
LE
12
XFER WR2 DGND
AGND
Rev. 2.00
1
MP1230A/31A/32A
ORDERING INFORMATION
www.DataSheet4U.com
Package
Type
Plastic Dip
Plastic Dip
Plastic Dip
SOIC
SOIC
SOIC
Temperature
Range
–40 to +85°C
–40 to +85°C
–40 to +85°C
–40 to +85°C
–40 to +85°C
–40 to +85°C
Part No.
MP1230ABN
MP1231ABN
MP1232ABN
MP1230ABS
MP1231ABS
MP1232ABS
INL
(LSB)
+1/2
+1
+2
+1/2
+1
+2
DNL
(LSB)
+3/4
+1
+2
+3/4
+1
+2
Gain Error
(% FSR)
+0.4
+0.4
+0.4
+0.4
+0.4
+0.4
PIN CONFIGURATIONS See Packaging Section for Package Dimensions
CS
WR1
AGND
DB7
DB6
DB5
DB4
VREF
RFB
DGND
1
2
3
4
5
6
7
8
9
10
20 VDD
19 BYTE1/BYTE2
18 WR2
17 XFER
16 DB8 (DB0, LSB)
15 DB9 (DB1)
14 DB10 (DB2)
13 DB11 MSB (DB3)
12 IOUT2
11 IOUT1
20 Pin PDIP (0.300”)
N20
CS
WR1
AGND
DB7
DB6
DB5
DB4
VREF
RFB
DGND
1
2
3
4
5
6
7
8
9
10
20 VDD
19 BYTE1/BYTE2
18 WR2
17 XFER
16 DB8 (DB0, LSB)
15 DB9 (DB1)
14 DB10 (DB2)
13 DB11 MSB (DB3)
12 IOUT2
11 IOUT1
20 Pin SOIC (Jedec, 0.300”)
S20
PIN OUT DEFINITIONS
PIN NO. NAME
DESCRIPTION
1 CS
2 WR1
3 AGND
4 DB7
5 DB6
6 DB5
7 DB4
8 VREF
9 RFB
10 DGND
11 IOUT1
Chip Select (Active Low)
Write 1 (Active Low)
Analog Ground
Data Input Bit 7
Data Input Bit 6
Data Input Bit 5
Data Input Bit 4
Reference Input Voltage
Feedback Resistor
Digital Ground
Current Output 1
Rev. 2.00
PIN NO. NAME
DESCRIPTION
12 IOUT2
Current Output 2
13 DB11 (DB3) Data Input Bit 11 (MSB)
Data Input Bit 3
14 DB10 (DB2) Data Input Bit 10
Data Input Bit 2
15 DB9 (DB1) Data Input Bit 9
Data Input Bit 1
16 DB8 (DB0) Data Input Bit 8
Data Input Bit 0 (LSB)
17 XFER
Transfer Control Signal (Active Low)
18 WR2
Write 2 (Active Low)
19 BYTE1/
BYTE2
Byte Sequence Control
20 VDD
Positive Power Supply
2
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