ADuC842 반도체 회로 부품 판매점
MicroConverter 12-Bit ADCs and DACs
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 Analog Devices |
Data Sheet
MicroConverter 12-Bit ADCs and DACs with
Embedded High Speed 62 kB Flash MCU
ADuC841/ADuC842/ADuC843
FEATURES
Pin compatible upgrade of ADuC812/ADuC831/ADuC832
Increased performance
Single-cycle 20 MIPS 8052 core
High speed 420 kSPS 12-bit ADC
Increased memory
Up to 62 kBytes on-chip Flash/EE program memory
4 kBytes on-chip Flash/EE data memory
In-circuit reprogrammable
Flash/EE, 100 year retention, 100 kCycle endurance
2304 bytes on-chip data RAM
Smaller package
8 mm × 8 mm chip scale package
52-lead PQFP—pin-compatible upgrade
Analog I/O
8-channel, 420 kSPS high accuracy, 12-bit ADC
On-chip, 15 ppm/°C voltage reference
DMA controller, high speed ADC-to-RAM capture
Two 12-bit voltage output DACs1
Dual output PWM ∑-∆ DACs
On-chip temperature monitor function
8052 based core
8051 compatible instruction set (20 MHz max)
High performance single-cycle core
32 kHz external crystal, on-chip programmable PLL
12 interrupt sources, 2 priority levels
Dual data pointers, extended 11-bit stack pointer
On-chip peripherals
Time interval counter (TIC)
UART, I2C®, and SPI® Serial I/O
Watchdog timer (WDT)
Power supply monitor (PSM)
Power
Normal: 4.5 mA @ 3 V (core CLK = 2.098 MHz)
Power-down: 10 μA @ 3 V2
Development tools
Low cost, comprehensive development system
incorporating nonintrusive single-pin emulation,
IDE based assembly and C source debugging
APPLICATIONS
Optical networking—laser power control
Base station systems
Precision instrumentation, smart sensors
Transient capture systems
DAS and communications systems
1 ADuC841/ADuC842 only.
2 ADuC842/ADuC843 only, ADuC841 driven directly by external crystal.
Rev. A
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
ADuC841/ADuC842/ADuC843
12-BIT
DAC
BUF
DAC1
ADC0
ADC1
ADC5
ADC6
ADC7
MUX
T/H
TEMP
SENSOR
12-BIT ADC
HARDWARE
CALIBRATON
12-BIT
DAC
16-BIT
- DAC
16-BIT
- DAC
16-BIT
PWM
16-BIT
PWM
BUF
DAC1
MUX
PWM0
PWM1
INTERNAL
BAND GAP
VREF
PLL2
OSC
20 MIPS 8052 BASED MCU WITH ADDITIONAL
PERIPHERALS
62 kBYTES FLASH/EE PROGRAM MEMORY
4 kBYTES FLASH/EE DATA MEMORY
2304 BYTES USER RAM
3 16 BIT TIMERS POWER SUPPLY MON
1 REAL TIME CLOCK WATCHDOG TIMER
4 PARALLEL
PORTS
UART, I2 C, AND SPI
SERIAL I/O
CREF
XTAL1 XTAL2
Figure 1.
GENERAL DESCRIPTION
The ADuC841/ADuC842/ADuC8431 are complete smart
transducer front ends, that integrates a high performance self-
calibrating multichannel ADC, a dual DAC, and an optimized
single-cycle 20 MHz 8-bit MCU (8051 instruction set compatible)
on a single chip.
The ADuC841 and ADuC842 are identical with the exception
of the clock oscillator circuit; the ADuC841 is clocked directly
from an external crystal up to 20 MHz whereas the ADuC842
uses a 32 kHz crystal with an on-chip PLL generating a
programmable core clock up to 16.78 MHz.
The ADuC843 is identical to the ADuC842 except that the
ADuC843 has no analog DAC outputs.
The microcontroller is an optimized 8052 core offering up to
20 MIPS peak performance. Three different memory options
are available offering up to 62 kBytes of nonvolatile Flash/EE
program memory. Four kBytes of nonvolatile Flash/EE data
memory, 256 bytes RAM, and 2 kBytes of extended RAM are
also integrated on-chip.
1 Protected by U.S. Patent No. 5,969,657.
(continued on page 15)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuC841/ADuC842/ADuC843
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Terminology .................................................................................... 19
ADC Specifications .................................................................... 19
DAC Specifications..................................................................... 19
Typical Performance Characteristics ........................................... 20
Functional Description .................................................................. 24
8052 Instruction Set ................................................................... 24
Other Single-Cycle Core Features ............................................ 26
Memory Organization ............................................................... 27
Special Function Registers (SFRs)............................................ 28
Accumulator SFR (ACC)........................................................... 29
Special Function Register Banks .............................................. 30
ADC Circuit Information.......................................................... 31
Calibrating the ADC .................................................................. 38
Nonvolatile Flash/EE Memory ................................................. 39
Using Flash/EE Data Memory .................................................. 42
REVISION HISTORY
4/16—Rev. 0 to Rev. A
Added Patent Note, Note 1.............................................................. 1
Changes to Figure 3 and Table 3..................................................... 9
Changes to Figure 4........................................................................ 14
Added Table 4; Renumbered Sequentially .................................. 14
Data Sheet
User Interface to On-Chip Peripherals.................................... 46
On-Chip PLL .............................................................................. 49
Pulse-Width Modulator (PWM).............................................. 50
Serial Peripheral Interface (SPI)............................................... 53
I2C Compatible Interface........................................................... 56
Dual Data Pointer....................................................................... 59
Power Supply Monitor ............................................................... 60
Watchdog Timer......................................................................... 61
Time Interval Counter (TIC).................................................... 62
8052 Compatible On-Chip Peripherals................................... 65
Timer/Counter 0 and 1 Operating Modes.............................. 70
Timer/Counter Operating Modes............................................ 72
UART Serial Interface................................................................ 73
SBUF ............................................................................................ 73
Interrupt System ......................................................................... 78
Hardware Design Considerations ............................................ 80
Other Hardware Considerations .............................................. 84
Development Tools .................................................................... 85
QuickStart Development System ............................................. 85
Timing Specifications, , .................................................................. 86
Outline Dimensions ....................................................................... 94
Ordering Guide .......................................................................... 95
Changes to Using the DAC Section ............................................. 47
Updated Outline Dimensions....................................................... 94
Changes to Ordering Guide .......................................................... 95
11/03—Revision 0: Initial Version
Rev. A | Page 2 of 95
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