MC56F8002 반도체 회로 부품 판매점
(MC56F8002 / MC56F8006) Digital Signal Controller
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 Freescale Semiconductor |
Freescale Semiconductor
Preliminary Technical Data
Document Number: MC56F8006
Rev. 2, 03/2009
MC56F8006/MC56F8002
www.datasheet4u.com
MC56F8006/MC56F8002
Digital Signal Controller
48-pin LQFP
Case: 932-03
7 x 7 mm2
28-pin SOIC
Case: 751F-05
7.5 x 18 mm2
32-pin LQFP
Case: 873A-03
7 x 7 mm2
The 56F8006/56F8002 is a member of the 56800E core-based
family of digital signal controllers (DSCs). It combines, on a
single chip, the processing power of a DSP and the
functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective solution.
Because of its low cost, configuration flexibility, and compact
program code, the 56F8006/56F8002 is well-suited for many
applications. The 56F8006/56F8002 includes many
peripherals that are especially useful for cost-sensitive
applications, including:
• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Switched-mode power supply and power management
• Power metering
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical device/equipment
• Instrumentation
• Lighting ballast
The 56800E core is based on a dual Harvard-style architecture
consisting of three execution units operating in parallel,
allowing as many as six operations per instruction cycle. The
MCU-style programming model and optimized instruction set
allow straightforward generation of efficient, compact DSP
and control code. The instruction set is also highly efficient
for C compilers to enable rapid development of optimized
control applications.
The 56F8006/56F8002 supports program execution from
internal memories. Two data operands can be accessed from
the on-chip data RAM per instruction cycle. The
56F8006/56F8002 also offers up to 40 general-purpose
input/output (GPIO) lines, depending on peripheral
configuration.
The 56F8006/56F8002 digital signal controller includes up to
16 KB of program flash and 2 KB of unified data/program
RAM. Program flash memory can be independently bulk
erased or erased in small pages of 512 bytes (256 words).
On-chip features include:
• Up to 32 MIPS at 32 MHz core frequency
• DSP and MCU functionality in a unified, C-efficient
architecture
• On-chip memory
– 56F8006: 16 KB (8K x 16) flash memory
– 56F8002: 12 KB (6K x 16) flash memory
– 2 KB (1K x 16) unified data/program RAM
• One 6-channel PWM module
• Two 28-channel, 12-bit analog-to-digital converters
(ADCs)
• Two programmable gain amplifiers (PGA) with gain up to
32x
• Three analog comparators
• One programmable interval timer (PIT)
• One high-speed serial communication interface (SCI) with
LIN slave functionality
• One serial peripheral interface (SPI)
• One 16-bit dual timer (2 x 16 bit timers)
• One programmable delay block (PDB)
• One SMBus compatible inter-integrated circuit (I2C) port
• One real time counter (RTC)
• Computer operating properly (COP)/watchdog
• Two on-chip relaxation oscillators — 1 kHz and 8 MHz
(400 kHz at standby mode)
• Crystal oscillator
• Integrated power-on reset (POR) and low-voltage interrupt
(LVI) module
• JTAG/enhanced on-chip emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 40 GPIO lines
• 28-pin SOIC, 32-pin LQFP, and 48-pin LQFP packages
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1 MC56F8006/MC56F8002 Family Configuration . . . . . . . . . . . .3
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
www.datash3e.1et4u5.6cFom8006/56F8002 Features . . . . . . . . . . . . . . . . . . . . . .4
3.2 Award-Winning Development Environment. . . . . . . . . . .8
3.3 Architecture Block Diagram. . . . . . . . . . . . . . . . . . . . . . .9
3.4 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . .11
4 Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . .11
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.3 56F8006/56F8002 Signal Pins . . . . . . . . . . . . . . . . . . .16
5 Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.2 Program Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.3 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.4 Interrupt Vector Table and Reset Vector . . . . . . . . . . . .30
5.5 Peripheral Memory-Mapped Registers . . . . . . . . . . . . .31
5.6 EOnCE Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .32
6 General System Control Information . . . . . . . . . . . . . . . . . . .33
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.2 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.3 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.4 On-chip Clock Synthesis . . . . . . . . . . . . . . . . . . . . . . . .33
6.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
6.6 System Integration Module (SIM) . . . . . . . . . . . . . . . . .36
6.7 PWM, PDB, PGA, and ADC Connections. . . . . . . . . . .37
6.8 Joint Test Action Group (JTAG)/Enhanced On-Chip
Emulator (EOnCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
7 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
7.1 Operation with Security Enabled. . . . . . . . . . . . . . . . . .39
7.2 Flash Access Lock and Unlock Mechanisms . . . . . . . .39
7.3 Product Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40
8.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 41
8.3 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 42
8.4 Recommended Operating Conditions . . . . . . . . . . . . . 44
8.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 45
8.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . 49
8.7 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . 50
8.8 External Clock Operation Timing. . . . . . . . . . . . . . . . . 51
8.9 Phase Locked Loop Timing . . . . . . . . . . . . . . . . . . . . . 51
8.10 Relaxation Oscillator Timing . . . . . . . . . . . . . . . . . . . . 52
8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing. 53
8.12 External Oscillator (XOSC) Characteristics . . . . . . . . . 53
8.13 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 54
8.14 COP Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.15 PGA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.16 ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.17 HSCMP Specifications . . . . . . . . . . . . . . . . . . . . . . . . 65
8.18 Optimize Power Consumption . . . . . . . . . . . . . . . . . . . 65
9 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . 67
9.2 Electrical Design Considerations. . . . . . . . . . . . . . . . . 68
9.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10 Package Mechanical Outline Drawings . . . . . . . . . . . . . . . . . 70
10.1 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2 32-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.3 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Appendix A
Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Appendix B
Peripheral Register Memory Map and Reset Value . . . . . . . 80
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2
2 Freescale Semiconductor
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MC56F8002 controller
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관련 데이터시트
MC56F8002
(MC56F8002 / MC56F8006) Digital Signal Controller - Freescale Semiconductor
MC56F8006
(MC56F8002 / MC56F8006) Digital Signal Controller - Freescale Semiconductor