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PSD303-B-70J 반도체 회로 부품 판매점

Low Cost Field Programmable Microcontroller Peripherals



ST Microelectronics 로고
ST Microelectronics
PSD303-B-70J 데이터시트, 핀배열, 회로
PSD3XX ZPSD3XX ZPSD3XXV
PSD3XXR ZPSD3XXR ZPSD3XXRV
Low Cost Field Programmable Microcontroller Peripherals
FEATURES SUMMARY
s Single Supply Voltage:
– 5 V±10% for PSD3xx, ZPSD3xx, PSD3xxR,
ZPSD3xxR
– 2.7 to 5.5 V for ZPSD3xxV, ZPSD3xxRV
s Up to 1 Mbit of EPROM
s Up to 16 Kbit SRAM
s Input Latches
s Programmable I/O ports
s Page Logic
s Programmable Security
Figure 1. Packages
PLDCC44 (J)
CLDCC44 (L)
PQFP44 (M)
TQFP44 (U)
January 2002
1/3


PSD303-B-70J 데이터시트, 핀배열, 회로
PSD3XX Family
PSD3XX ZPSD3XX ZPSD3XXV
PSD3XXR ZPSD3XXR ZPSD3XXRV
Low Cost Microcontroller Peripherals
Table of Contents
1 Introduction ...........................................................................................................................................................1
2 Notation ................................................................................................................................................................2
3 Key Features ........................................................................................................................................................4
4 PSD3XX Family Feature Summary ......................................................................................................................5
5 Partial Listing of Microcontrollers Supported ........................................................................................................6
6 Applications ..........................................................................................................................................................6
7 ZPSD Background ................................................................................................................................................6
7.1 Integrated Power ManagementTM Operation .............................................................................................7
8 Operating Modes (MCU Configurations) ............................................................................................................10
9 Programmable Address Decoder (PAD).............................................................................................................12
10 I/O Port Functions ...............................................................................................................................................15
10.1 CSIOPORT Registers..............................................................................................................................15
10.2 Port A (PA0-PA7).....................................................................................................................................16
10.2.1 Port A (PA0-PA7) in Multiplexed Address/Data Mode................................................................16
10.2.2 Port A (PA0-PA7) in Non-Multiplexed Address/Data Mode ........................................................17
10.3 Port B (PB0-PB7).....................................................................................................................................18
10.3.1 Port B (PA0-PA7) in Multiplexed Address/Data Mode................................................................18
10.3.2 Port B (PA0-PA7) in Non-Multiplexed Address/Data Mode ........................................................19
10.4 Port C (PC0-PC2) ....................................................................................................................................20
10.5 ALE/AS Input Pin .....................................................................................................................................20
11 PSD Memory ......................................................................................................................................................21
11.1 EPROM....................................................................................................................................................21
11.2 SRAM (Optional)......................................................................................................................................21
11.3 Page Register (Optional) .........................................................................................................................21
11.4 Programming and Erasure.......................................................................................................................21
12 Control Signals ...................................................................................................................................................22
12.1 ALE or AS ................................................................................................................................................22
12.2 WR or R/W...............................................................................................................................................22
12.3 RD/E/DS (DS option not available on 3X1 devices) ................................................................................22
12.4 PSEN or PSEN ........................................................................................................................................22
12.5 A19/CSI ...................................................................................................................................................23
12.6 Reset Input ..............................................................................................................................................24
13 Program/Data Space and the 8031 ....................................................................................................................26
14 Systems Applications..........................................................................................................................................27
15 Security Mode .....................................................................................................................................................30
16 Power Management............................................................................................................................................30
16.1 CSI Input..................................................................................................................................................30
16.2 CMiser Bit ................................................................................................................................................30
16.3 Turbo Bit (ZPSD Only).............................................................................................................................31
16.4 Number of Product Terms in the PAD Logic............................................................................................31
16.5 Composite Frequency of the Input Signals to the PAD Logic..................................................................32
16.6 Loading on I/O Pins .................................................................................................................................33
17 Calculating Power ...............................................................................................................................................34
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