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Low Cost Field Programmable Microcontroller Peripherals



STMicroelectronics 로고
STMicroelectronics
ZPSD501B1V-C-20J 데이터시트, 핀배열, 회로
PSD5XX
ZPSD5XX
Low Cost Field Programmable Microcontroller Peripherals
NOT FOR NEW DESIGN
FEATURES SUMMARY
s Single Supply Voltage:
– 5 V±10% for PSD5XX
– 2.7 to 5.5 V for PSD5XX-V
s Up to 1 Mbit of UV EPROM
s Up to 16 Kbit SRAM
s Input Latches
s Programmable I/O ports
s Page Logic
s Programmable Security
Figure 1. Packages
PLDCC68 (J)
CLDCC68 (L)
TQFP68 (U)
January 2002
This is information on a product still in production but not recommended for new designs.
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ZPSD501B1V-C-20J 데이터시트, 핀배열, 회로
PSD5XX Family
PSD5XX/ZPSD5XX
Field-Programmable Microcontroller Peripherals
Table of Contents
1 Introduction ...........................................................................................................................................................1
2 Key Features ........................................................................................................................................................3
3 Notation ................................................................................................................................................................4
4 ZPSD Background ................................................................................................................................................4
5 Integrated Power ManagementTM Operation ........................................................................................................6
6 Design Flow ..........................................................................................................................................................7
7 PSD5XX Family ....................................................................................................................................................8
8 Table 2. PSD5XX Pin Descriptions......................................................................................................................9
9 The PSD5XX Architecture ..................................................................................................................................11
9.1 The ZPLD Block..........................................................................................................................................11
9.1.1 The DPLD.........................................................................................................................................14
9.1.2 The GPLD.........................................................................................................................................14
9.1.2.1 Por A Macrocell Structure ..................................................................................................16
9.1.2.2 Port B Macrocell Structure .................................................................................................20
9.1.2.3 Port E Macrocell Structure .................................................................................................23
9.1.3 The PPLD .........................................................................................................................................26
9.1.4 The ZPLD Power Management ........................................................................................................26
9.2 Bus Interface...............................................................................................................................................29
9.2.1 Bus Interface Configuration ..............................................................................................................29
9.2.2 PSD5XX Interface to a Multiplexed Bus ...........................................................................................29
9.2.3 PSD5XX Interface to Non-Multiplexed Bus ......................................................................................30
9.2.4 Data Byte Enable..............................................................................................................................30
9.2.5 Optional Features .............................................................................................................................34
9.2.6 Bus Interface Examples....................................................................................................................34
9.3 I/O Ports......................................................................................................................................................39
9.3.1 Standard MCU I/O ............................................................................................................................39
9.3.2 PLD I/O ...........................................................................................................................................39
9.3.3 Address Out......................................................................................................................................40
9.3.4 Address In ........................................................................................................................................40
9.3.5 Data Port ..........................................................................................................................................40
9.3.6 Special Function Out ........................................................................................................................40
9.3.7 Alternate Function In ........................................................................................................................41
9.3.8 Peripheral I/O ...................................................................................................................................41
9.3.9 Open Drain Outputs..........................................................................................................................41
9.3.10 Port Registers...................................................................................................................................42
9.3.11 Port A – Functionality and Structure.................................................................................................45
9.3.12 Port B – Functionality and Structure.................................................................................................45
9.3.13 Port C and Port D – Functionality and Structure ..............................................................................48
9.3.14 Port E – Functionality and Structure.................................................................................................48
9.4 Memory Block .............................................................................................................................................52
9.4.1 EPROM ............................................................................................................................................52
9.4.2 SRAM ...............................................................................................................................................52
9.4.3 Memory Select Map..........................................................................................................................52
9.4.4 Memory Select Map for 8031 Application.........................................................................................54
9.4.5 Peripheral I/O ...................................................................................................................................56
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