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TEMIC Semiconductors |
8-bit CMOS Microcontroller 0-60 MHz
TS80C52X2
1. Description
TEMIC TS80C52X2 is high performance CMOS ROM,
OTP, EPROM and ROMless versions of the 80C51
CMOS single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the TEMIC
80C51 with extended ROM/EPROM capacity (8
Kbytes), 256 bytes of internal RAM, a 6-source , 4-level
interrupt system, an on-chip oscilator and three timer/
counters.
In addition, the TS80C52X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C52X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C52X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q 80C52 Compatible
• 8051 pin and instruction compatible
• Four 8-bit I/O ports
• Three 16-bit timer/counters
• 256 bytes scratchpad RAM
q High-Speed Architecture
• 40 MHz @ 5V, 30MHz @ 3V
• X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
q Dual Data Pointer
q On-chip ROM/EPROM (8K-bytes)
q Programmable Clock Out and Up/Down Timer/
Counter 2
q Asynchronous port reset
q Interrupt Structure with
• 6 Interrupt sources,
• 4 level priority interrupt system
q Full duplex Enhanced UART
• Framing error detection
• Automatic address recognition
q Low EMI (inhibit ALE)
q Power Control modes
• Idle mode
• Power-down mode
• Power-off Flag
q Once mode (On-chip Emulation)
q Power supply: 4.5-5V, 2.7-5.5V
q Temperature ranges: Commercial (0 to 70oC) and
Industrial (-40 to 85oC)
q Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1
(13.9 footprint), CQPJ44 (window), CDIL40
(window)
Rev. B - Jan. 25, 1999
Preliminary
1
TS80C52X2
TS80C32X2
TS80C52X2
TS87C52X2
3. Block Diagram
Table 1. Memory size
ROM (bytes)
0
8k
0
EPROM (bytes)
0
0
8k
TOTAL RAM
(bytes)
256
256
256
XTAL1
XTAL2
ALE/ PROG
PSEN
EA/VPP
RD
WR
(3)
(3)
(3) (3)
EUART
RAM
256x8
ROM
/EPROM
8Kx8
CPU
C51
CORE
IB-bus
(1) (1)
Timer2
Timer 0
Timer 1
INT
Ctrl
(3) (3) (3) (3)
Parallel I/O Ports & Ext. Bus
Port 0 Port 1 Port 2 Port 3
(1): Alternate function of Port 1
(2): Only available on high pin count packages
(3): Alternate function of Port 3
2 Rev. B - Jan. 25, 1999
Preliminary
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