Am53CF94JCW 반도체 회로 부품 판매점
Enhanced SCSI-2 Controller (ESC)
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 Advanced Micro Devices |
PRELIMINARY
Am53CF94/Am53CF96
Enhanced SCSI-2 Controller (ESC)
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s Pin/function compatible with Emulex
FAS216/236
s AMD’s Patented programmable GLITCH
EATERTM Circuitry on REQ and ACK inputs
s 10 Mbytes/s synchronous Fast SCSI transfer
rate
s 20 Mbytes/s DMA transfer rate
s 16-Bit DMA interface plus 2 bits of parity
s Flexible three bus architecture
s Single-ended SCSI bus supported by
Am53CF94
s Differential SCSI bus supported by Am53CF96
s Selection of multiplexed or non-multiplexed
address and data bus
s High current drivers (48 mA) for direct
connection to the single-ended SCSI bus
s Supports Disconnect and Reselect commands
s Supports burst mode DMA operation with a
threshold of eight
s Supports 3-byte tagged-queueing as per the
SCSI-2 specification
s Supports group 2 and 5 command recognition
as per the SCSI-2 specification
s Advanced CMOS process for lower power
consumption
GENERAL DESCRIPTION
The Enhanced SCSI-2 Controller (ESC) was designed
to support Fast SCSI-2 transfer rates of up to
10 Mbytes/s in synchronous mode and up to 7 Mbytes/s
in the asynchronous mode. The ESC is downward com-
patible with the Am53C94/96, combining its functionality
with features such as Fast SCSI, programmable Active
Negation, a 24-bit transfer counter, and a part-unique ID
code containing manufacturer and serial # information.
AMD’s proprietary features such as power-down mode
for SCSI transceivers, programmable GLITCH EATER,
and extended Target command set are also included for
improved product performance.
The Enhanced SCSI-2 Controller (ESC) has a flexible
three bus architecture. The ESC has a 16-bit DMA inter-
face, an 8-bit host data interface and an 8-bit SCSI data
interface. The ESC is designed to minimize host inter-
vention by implementing common SCSI sequences in
hardware. An on-chip state machine reduces protocol
overheads by performing the required sequences in re-
sponse to a single command from the host. Selection,
s AMD’s exclusive programmable power-down
feature
s 24-Bit extended transfer counter allows for
data block transfer of up to 16 Mbytes
s Independently programmable 3-byte message
and group 2 identification
s Additional check for ID message during
bus-initiated Select with ATN
s Reselection has QTAG features of ATN3
s Access FIFO Command
s Delayed enable signal for differential drivers
avoid contention on SCSI differential lines
s Programmable Active Negation on REQ, ACK
and Data lines
s Register programmable control of assertion/
deassertion delay for REQ and ACK lines
s Part-unique ID code
s Am53CF94 available in 84-pin PLCC package
s Am53CF96 available in 100-pin PQFP package
s Am53CF94 available in 3.3 V version
s Supports clock operating frequencies from
10 MHz–40 MHz
s Supports Scatter-Gather or Back-to-Back
synchronous data transfers
reselection, information transfer and disconnection
commands are directly supported.
The 16-byte-internal FIFO further assists in minimizing
host involvement. The FIFO provides a temporary stor-
age for all command, data, status and message bytes as
they are transferred between the 16-bit host data bus
and the 8-bit SCSI data bus. During DMA operations the
FIFO acts as a buffer to allow greater latency in the DMA
channel. This permits the DMA channel to be sus-
pended for higher priority operations such as DRAM re-
fresh or reception of an ISDN packet.
Parity on the DMA bus is optional. Parity can either be
generated and checked or it can be simply passed
through.
The Target command set for the Am53CF94/96 in-
cludes an additional command, the Access FIFO com-
mand, to allow the host or DMA controller to remove re-
maining FIFO data following the host’s issuance of a
Target abort DMA command or following an abort due to
This document contains information on a product under development at Advanced Micro Devices Inc. The information is intended Publication# 17348 Rev. B Amendment /0
to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Issue Date: May 1993
AMD
PRELIMINARY
parity error. This command facilitates data recovery and
thereby minimizes the need to re-transmit data.
AMD’s exclusive power-down feature can be enabled to
help reduce power consumption during the chip’s sleep
mode. The receivers on the SCSI bus may be turned off
to eliminate current that may flow because termination
power (~3 V) is close to the trip point of the input buffers.
The patented GLITCH EATER Circuitry in the
Enhanced SCSI-2 Controller can be programmed to
filter glitches with widths up to 35 ns. It is designed to
dramatically increase system reliability by detecting and
removing glitches that may cause system failure. The
GLITCH EATER Circuitry is implemented on the ACK
and REQ lines since they are most susceptible to
electrical anomalies such as reflections and voltage
spikes. Such signal inconsistencies can trigger false
REQ/ACK handshaking, false data transfers, addition of
random data, and double clocking. AMD’s GLITCH
EATER Circuitry therefore maintains system perform-
ance and improves reliability. The following diagram
illustrates this circuit’s operation.
The Am53CF94 is also available in a 3.3 V version.
GLITCH EATER Circuitry in SCSI Environment
SCSI Environment
Device without the
GLITCH EATER Circuit
AMD’s Device with the
GLITCH EATER Circuit
Glitch Window
Note:
The Glitch Window is programmable via Control Register Four (0DH), bits 6 & 7. Window may be set to 35 ns (max). Default
setting is 12 ns (single-ended).
17348B-1
SYSTEM BLOCK DIAGRAM
CPU
DMA
4 Addr
16 8
Data Am53CF94/96
16
DMA
16
9 SCSI Data
9 SCSI Control
Memory
16
17348B-2
2 Am53CF94/Am53CF96
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Am53CF94JCW controller
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Am53CF94JC
Enhanced SCSI-2 Controller (ESC) - Advanced Micro Devices
Am53CF94JCW
Enhanced SCSI-2 Controller (ESC) - Advanced Micro Devices