HS1-82C85RH-Q 반도체 회로 부품 판매점
Radiation Hardened CMOS Static Clock Controller/Generator
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 Intersil Corporation |
HS-82C85RH
August 1995
Radiation Hardened
CMOS Static Clock Controller/Generator
Features
Pinouts
• Radiation Hardened
- Total Dose > 105 RAD (Si)
- Transient Upset > 108 RAD (Si)/s
- Latch Up Free EPI-CMOS
• Very Low Power Consumption
• Pin Compatible with NMOS 8285 and Intersil 82C85
• Generates System Clocks for Microprocessors and Peripherals
• Complete Control Over System Clock Operation for Very Low
System Power
- Stop-Oscillator
- Stop-Clock
- Low Frequency (Slo) Mode
- Full Speed Operation
• DC to 15MHz Operation (DC to 5MHz System Clock)
• Generates Both 50% and 33% Duty Cycle Clocks (Synchronized)
• Uses Either Parallel Mode Crystal Circuit or External Frequency
Source
• Hardened Field, Self-Aligned, Junction Isolated CMOS Process
• Single 5V Supply
• Military Temperature Range -55oC to +125oC
Description
The Intersil HS-82C85RH is a high performance, radiation hardened
CMOS Clock Controller/Generator designed to support systems utilizing
radiation hardened static CMOS microprocessors such as the
HS-80C86RH. The HS-82C85RH contains a crystal controlled oscillator,
reset pulse conditioning, halt/restart logic, and divide-by-256 circuitry.
These features provide the means to stop the system clock, stop the clock
oscillator, or run the system at a low frequency (CLK/256), enhancing
control of static system power dissipation and allowing system shut-down
during periods of external stress.
Static CMOS circuit design insures low operating power and permits
operation with an external frequency source from DC to 15MHz. Crystal
controlled operation to 15MHz is guaranteed with the use of a parallel,
fundamental mode crystal and two small load capacitors. Outputs are
guaranteed compatible with both CMOS and TTL specifications. The Inter-
sil hardened field CMOS process results in performance equal to or
greater than existing radiation resistant products at a fraction of the power.
24 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
CLK50 10
START 11
SLO/FST 12
24 VDD
23 X1
22 X2
21 ASYNC
20 EFI
19 F/C
18 OSC
17 RES
16 RESET
15 S2/STOP
14 S1
13 S0
24 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
CSYNC
PCLK
AEN1
RDY1
READY
RDY2
AEN2
CLK
GND
CLK50
START
SLO/FST
1
2
3
4
5
6
7
8
9
10
11
12
24 VDD
23 X1
22 X2
21 ASYNC
20 EFI
19 F/C
18 OSC
17 RES
16 RESET
15 S2/STOP
14 S1
13 S0
Ordering Information
PART NUMBER
HS1-82C85RH-Q
HS1-82C85RH-8
HS1-82C85RH/Sample
HS9-82C85RH/Proto
HS9-82C85RH-Q
HS9-82C85RH-8
HS9-82C85RH/Sample
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
+25oC
PACKAGE
24 Lead SBDIP
24 Lead SBDIP
24 Lead SBDIP
24 Lead Ceramic Flatpack
24 Lead Ceramic Flatpack
24 Lead Ceramic Flatpack
24 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
992
Spec Number 518061
File Number 3044.1
Pin Description
PIN
PIN NUMBER
X1 23
X2 22
EFI 20
F/C 19
START
11
S0
S1
S2/STOP
13
14
15
SLO/FST
12
CLK 8
CLK50
10
PCLK
OSC
2
18
HS-82C85RH
TYPE
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DESCRIPTION
CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections. The crystal
frequency must be three times the maximum desired processor clock frequency. X1 is the
oscillator circuit input and X2 is the output of the oscillator circuit.
EXTERNAL FREQUENCY IN: When F/C is HIGH, CLK is generated from the EFI input signal.
This input signal should be a square wave with a frequency of three times the maximum desired
CLK output frequency.
FREQUENCY/CRYSTAL SELECT: F/C selects either the crystal oscillator or the EFI input as the
main frequency source. When F/C is LOW, the HS-82C85RH clocks are derived from the crystal
oscillator circuit. When F/C is HIGH, CLK is generated from the EFI input. F/C cannot be dynam-
ically switched during normal operation.
A low-to-high transition on START will restart the CLK, CLK50 and PCLK outputs after the
appropriate restart sequence is completed.
When in the crystal mode (F/C LOW) with the oscillator stopped, the oscillator will be restarted
when a Start command is received. The CLK, CLK50 and PCLK outputs will start after the oscil-
lator input signal (X1) reaches the Schmitt trigger input threshold and an 8K internal counter
reaches terminal count. If F/C is HIGH (EFI mode), CLK, CLK50 and PCLK will restart within 3 EFI
cycles after START is recognized.
The HS-82C85RH will restart in the same mode (SLO/FST) in which it stopped. A high level on
START disables the STOP mode.
S2/STOP, S1, S0 are used to stop the HS-82C85RH clock outputs (CLK, CLK50, PCLK) and are
sampled by the rising edge of CLK. CLK, CLK50 and PCLK are stopped by S2/STOP,S1, S0 being
in the LHH state on the low-to-high transition of CLK. This LHH state must follow a passive HHH
state occurring on the previous low-to-high CLK transition. CLK and CLK50 stop in the high state.
PCLK stops in it’s current state (high or low).
When in the crystal mode (F/C) low and a STOP command is issued, the HS-82C85RH oscillator
will stop along with the CLK, CLK50 and PCLK outputs. When in the EFI mode, only the CLK,
CLK50 and PCLK outputs will be halted. The oscillator circuit if operational, will continue to run.
The oscillator and/or clock is restarted by the START input signal going true (HIGH) or the reset
input (RES) going low.
SLO/FST is a level-triggered input. When HIGH, the CLK and CLK50 outputs run at the maximum
frequency (crystal or EFI frequency divided by 3). When LOW, CLK and CLK50 frequencies are
equal to the crystal or EFI frequency divided by 768. SLO/FST mode changes are internally
synchronized to eliminate glitches on the CLK and CLK50. START and STOP control of the
oscillator or EFI is available in either the SLOW or FAST frequency modes.
The SLO/FST input must be held LOW for at least 195 OSC/EFI clock cycles before it will be
recognized. This eliminates unwanted frequency changes which could be caused by glitches or
noise transients. The SLO/FST input must be held HIGH for at least 6 OSC/EFI clock pulses to
guarantee a transition to FAST mode operation.
PROCESSOR CLOCK: CLK is the clock output used by the HS-80C86RH processor and other
peripheral devices. When SLO/FST is high, CLK has an output frequency which is equal to the
crystal or EFI input frequency divided by three. When SLO/FST is low, CLK has an output frequen-
cy which is equal to the crystal or EFI input frequency divide by 768. CLK has a 33% duty cycle.
50% DUTY CYCLE CLOCK: CLK50 is an auxiliary clock with a 50% duty cycle and is synchro-
nized to the falling edge of CLK. When SLO/FST is high, CLK50 has an output frequency which
is equal to the crystal or EFI input frequency divided by 3. When SLO/FST is low, CLK50 has an
output frequency equal to the crystal or EFI input frequency divided by 768.
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is equal to the
crystal or EFI input frequency divided by six and has a 50% duty cycle. PCLK frequency is
unaffected by the state of the SLO/FST input.
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is
equal to that of the crystal oscillator circuit. OSC is unaffected by the state of the SLO/FST input.
When the HS-82C85RH is in the crystal mode (F/C LOW) and a STOP command is issued, the
OSC output will stop in the HIGH state. When the HS-82C85RH is in the EFI mode (F/C HIGH),
the oscillator (if operational) will continue to run when a STOP command is issued and OSC
remains active.
Spec Number 518061
993
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HS1-82C85RH-Q controller
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관련 데이터시트
HS1-82C85RH-8
Radiation Hardened CMOS Static Clock Controller/Generator - Intersil Corporation
HS1-82C85RH-Q
Radiation Hardened CMOS Static Clock Controller/Generator - Intersil Corporation