UPB8228 반도체 회로 부품 판매점
8080A SYSTEM CONTROLLER AND BUS DRIVER
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 NEC |
NEe Microcomputers, Inc.
fttIEC
Jl,PB8228
J.I PB8238
8080A SYSTEM CONTROLLER
AND BUS DRIVER
OESCR IPTION
The pPB8228/8238 is a single chip cOntroller and bus driver for 8080A based
systems. All the required interface signals rrecessary to connect RAM, ROM and
I/O components to a pPD8080A are generated.
The pPB8228/8238 provides a bi·directional three·state bus driver for high TTL
fan-out and isolation of the processor data bus from the system data bus for
increased noise immunity.
The system controller portion of the pPB8228/8238 consists of a status latch for
definition of processor machine cycles and a gating array to decode this information
for direct interface to system components. The controller can enable gating of a
multi·byte interrupt onto the data bus or can automatically insert a RESTART 7 Onto
the data bus without any additional components.
Two devices are provided:. the pPB8228 for small systems without tight write timing
constraints and the pPB8238 for larger systems.
FEATU RES
• System Controller for 8080A Systems
• Bi-Directional Data Bus for Processor Isolation
• 3.60V Output High Voltage for Direct Interface to 8080A Processor
•• Three State Outputs on System Data Bus
• Enables Use of Multi-Byte Interrupt Instructions
• Generates RST 7 Interrupt Instruction
• pPB8228 for Small Memory Systems
• pPB8238 for Large Memory Systems
• Reduces System Package Count
• Schottky Bipolar Technology
PIN CONFIGURATION
STSTB
HLDA
WR
DBIN
DB4
D4
DB7
D7
DB3
D3
DB2
D2
DBa
GND
NC: No Connection
Vee
I/OW
MEMW
I/OR
MEMR
INTA
BUSEN
DS
DBS
D5
DB5
D,
DB,
DO
PIN NAMES
07 - Do
DB7 DB
liaR
IIOW
MEMR
MEMW
DBIN
I'ITA
HLDA
WR
BUSEN
STSTB
Vec
GND
Data Bus (Processor Side)
Data Bus (System Si<!~
I/O Read
1/0 Write
Memory Read
Memory Write
OBI N (From ProcttliSOri
Interrupt Al:.knowledge
HLDA (From Processor)
WR (From Processorl
Bus Enabte Input
Status Strobe (From J.'PB8224)
+5V
OVohs
II
Rev/l
571
p.P 8822818238
Bi-Directional Bus Driver
The eight bit, bi-directional bus driver provides buffering between the processor data
bus and the syst~m data bus. On the processor side, the j1PB8228/8238 exceeds the
minimum input voltage requirements (3.0V) of the j1PD8080A. On the system side,
the driver is capable of adequate drive current (10 mAl for connection of a large
number of memory and 1/0 devices to the bus. Signal flow in the bus driver is con-
trolled by the gating array and its outputs can be forced into a high impedance state
by use of the BUSEN input.
Status Latch
The Status Latch in the j1PB8228/8238 stores the status information placed on the
data bus by the 8080A at the beginning of each machine cycle. The information is
latched when 'STSTB goes low and is then decoded by the gating array for the
generation of control signals.
Gating Array
The Gating Array generates "active low" control signals for direct interfacing to system
components by gating the contents of the status latch with control signals from the
8080A.
MEM/R, IIOR and INTA are generated by gating the DBIN signal from the processor
with the contents of the status latch. liaR is used to enable an 1/0 input onto the
system data bus. MEMIR is used to enable a memory input.
INTA is normally used to gate an interrupt instruction onto the system data bus. When
used with the j1PD8080A processor, the j1PB8228/8238 will decode an interrupt
acknowledge status word during all three machine cycles for a multi-byte interrupt
instruction. For 8080A type processors that do not generate an interrupt acknowledge
status word during the second and third machine cycles of a multi-byte interrupt
instruction, the j1PB8228/8238 will internally generate an INTA pulse for those
mach ine cycl es.
The j1PB822i.l/8238 also provides the designer the ability to place a single interrupt
instruction onto the bus without adding additional components. By connecting the
+12 volt supply to the INTA output (pin 23) of the j1PB8228/8238 through a 1 K
ohm series resistor, RESTART 7 will be gated onto the processor data bus when DBIN
is active during an interrupt acknowledge machine cycle.
MEM/W and IIOW are generated by gating the WR signal from the processor with the
contents of the status latch. IIOW indicates that an output port write is about to
occur. MEM/W indicates that a memory write will occur.
The data bus output buffers and control signal buffers can be asynchronously forced
into a high impedance state by placing a high on the BUSEN pin of the j1PB82281
8238. Normal operation is performed with BUSEN low.
DBO
DB,
FUNCTIONAL DESCRIPTION
BLOCK DIAGRAM
PROCESSOR
DATA
BUS
03
SYSTEM DATA BUS
vee@-
GNO@-I
STSTS(1) •
572
MEMR
MEMW
IIOR
I/OW
I3USEN
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UPB8228 controller
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