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MX29F200CB 반도체 회로 부품 판매점

2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY



Macronix International 로고
Macronix International
MX29F200CB 데이터시트, 핀배열, 회로
www.DataSheet4U.com
MX29F200C T/B
2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY
FEATURES
• 5.0V±10% for read, erase and write operation
• 131072x16/262144x8 switchable
• Fast access time: 55/70/90ns
Compatible with MX29F200T/B device
• Low power consumption
- 40mA maximum active current@5MHz
- 1uA typical standby current
• Command register architecture
- Byte/Word Programming (9us/11us typical)
- Sector Erase (16K-Bytex1, 8K-Bytex2, 32K-Bytex1,
and 64K-Byte x3)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors or
the whole chip with Erase Suspend capability.
- Automatically program and verify data at specified
address
• Status Reply
- Data# Polling & Toggle bit for detection of program
and erase cycle completion.
• Ready/Busy# pin(RY/BY#)
- Provides a hardware method or detecting program
or erase cycle completion
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
- Superior inadvertent write protection
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors
• Sector protect/chip unprotect for 5V only system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Erase suspend/ Erase Resume
- Suspends an erase operation to read data from, or
program data to a sector that is not being erased, then
resume the erase operation.
• Hardware reset pin
- Resets internal state mechine to the read mode
• 20 years data retention
• Package type:
- 44-pin SOP
- 48-pin TSOP
- All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
The MX29F200C T/B is a 2-mega bit, single 5 Volt Flash
memory organized as 1M word x16 or 2M bytex8 MXIC's
Flash memories offer the most cost-effective and reli-
able read/write non-volatile random access memory.
The MX29F200C T/B is packaged in 44-pin SOP and 48-
pin TSOP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.
The standard MX29F200C T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention, the
MX29F200C T/B has separate chip enable (CE#) and
output enable (OE# ) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F200C T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields for
erase and programming operations produces reliable
cycling. The MX29F200C T/B uses a 5.0V ±10% VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM1250
REV. 1.0, DEC. 14, 2005
1


MX29F200CB 데이터시트, 핀배열, 회로
PIN CONFIGURATIONS
44 SOP(500mil)
NC
RY/BY#
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RESET#
43 WE#
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
32 GND
31 Q15/A-1
30 Q7
29 Q14
28 Q6
27 Q13
26 Q5
25 Q12
24 Q4
23 VCC
MX29F200wwwC.DataShTeet4/U.Bcom
PIN DESCRIPTION
SYMBOL
A0-A16
Q0-Q14
Q15/A-1
CE#
OE#
RESET#
WE#
RY/BY#
BYTE#
VCC
GND
NC
PIN NAME
Address Input
Data Input/Output
Q15(Word mode)/LSB addr.(Byte mode)
Chip Enable Input
Output Enable Input
Hardware Reset Pin, Active low
Write Enable Input
Read/Busy Output
Word/Byte Selection Input
Power Supply Pin (+5V)
Ground Pin
Pin Not Connected Internally
48 TSOP(TYPE I) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MX29F200C T/B
(NORMAL TYPE)
48 A16
47 BYTE#
46 GND
45 Q15/A-1
44 Q7
43 Q14
42 Q6
41 Q13
40 Q5
39 Q12
38 Q4
37 VCC
36 Q11
35 Q3
34 Q10
33 Q2
32 Q9
31 Q1
30 Q8
29 Q0
28 OE#
27 GND
26 CE#
25 A0
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29F200C T/B
(REVERSE TYPE)
1 A15
2 A14
3 A13
4 A12
5 A11
6 A10
7 A9
8 A8
9 NC
10 NC
11 WE#
12 RESET#
13 NC
14 NC
15 RY/BY#
16 NC
17 NC
18 A7
19 A6
20 A5
21 A4
22 A3
23 A2
24 A1
P/N:PM1250
REV. 1.0 , DEC. 14, 2005
2




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MX29F200CB cmos

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