TC55V400AFT-55 반도체 회로 부품 판매점
16-BIT FULL CMOS STATIC RAM
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 Toshiba Semiconductor |
TC55V400AFT-55,-70
www.DataSheet4U.com TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55V400AFT is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16
bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6
V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5 mA standby
current (at VDD = 3 V, Ta = 25°C, maximum) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low.
There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and
output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte
access. This device is well suited to various microprocessor system applications where high speed, low power and
battery backup are required. And, with a guaranteed operating extreme temperature range of -40° to 85°C, the
TC55V400AFT can be used in environments exhibiting extreme temperature conditions. The TC55V400AFT is
available in normal and reverse pinout plastic 48-pin thin-small-outline package (TSOP).
FEATURES
· Low-power dissipation
Operating: 10.8 mW/MHz (typical)
· Single power supply voltage of 2.3 to 3.6 V
· Power down features using CE1 and CE2
· Data retention supply voltage of 1.5 to 3.6 V
· Direct TTL compatibility for all inputs and outputs
· Wide operating temperature range of -40° to 85°C
· Standby Current (maximum):
3.6 V
3.0 V
7 mA
5 mA
· Access Times (maximum):
TC55V400AFT
-55 -70
Access Time
55 ns
70 ns
CE1 Access Time
55 ns
70 ns
CE2 Access Time
55 ns
70 ns
OE Access Time
30 ns
35 ns
· Package:
TSOPⅠ48-P-1214-0.50 (AFT) (Weight: 0.38 g typ)
PIN ASSIGNMENT (TOP VIEW)
48 PIN TSOP
1 48
24 25
(Normal)
PIN NAMES
A0~A17
CE1 , CE2
R/W
OE
LB , UB
I/O1~I/O16
VDD
GND
NC
Address Inputs
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A15 A14 A13 A12 A11 A10 A9 A8 NC NC R/W CE2 NC UB LB NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A17 A7 A6 A5 A4 A3 A2 A1 A0 CE1 GND OE I/O1 I/O9 I/O2 I/O10
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
I/O3 I/O11 I/O4 I/O12 VDD I/O5 I/O13 I/O6 I/O14 I/O7 I/O15 I/O8 I/O16 GND NC A16
2001-09-04 1/11
www.DaBtaSLhOeeCt4KU.cDomIAGRAM
TC55V400AFT-55,-70
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
CE
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A17
MEMORY CELL ARRAY
2,048 ´ 128 ´ 16
(4,194,304)
VDD
GND
SENSE AMP
CLOCK
GENERATOR
COLUMN ADDRESS
DECODER
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
CE
A0 A1 A2 A3 A14 A15 A16
R/W
OE
UB
LB
CE1
CE2
CE
OPERATING MODE
MODE
Read
Write
Output Deselect
Standby
* = don't care
H = logic high
L = logic low
CE1 CE2 OE R/W LB
L
L H L HH
L
L
LH* LH
L
LHHH *
LH* *H
H* * * *
*L***
UB I/O1~I/O8
L Output
L High-Z
H Output
L Input
L High-Z
H Input
*
High-Z
H
*
High-Z
*
I/O9~I/O16
Output
Output
High-Z
Input
Input
High-Z
High-Z
High-Z
POWER
IDDO
IDDO
IDDO
IDDO
IDDO
IDDO
IDDO
IDDS
2001-09-04 2/11
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제조업체: Toshiba Semiconductor
( toshiba )
TC55V400AFT-55 cmos
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[ TC55V400AFT-55.PDF ]
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