ATC18RHA 반도체 회로 부품 판매점
Rad. Hard 0.18 Um CMOS Cell-based ASIC for Space Use
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 ATMEL Corporation |
Features
• Comprehensive Library of Standard Logic and I/O Cells
• ATC18RHA Core and I/O Cells Designed to Operate with VDD = 1.8V Sparing 0.15V as
Main Target Operating Conditions
• IO33 Pad Libraries Provide Interfaces to 3V Environments
• Memory Cells Compiled to the Precise Requirements of the Design
• EDAC Library
• SEU Hardened DFF’s
• Cold Sparring Buffers
• High Speed LVDS Buffers
• PCI Buffers
• Predefined Die Sizes to Accommodate Specified Packages and ESA (European Space
Agency) Multi-project Wafer Services
• MQFP Package Up to 352 Pins (340 Signal Pins)
• MCGA Packages Up to 625 Pins (581 Signal Pins)
• Assurance Programs Will Allow
– Testing Flight Models to SCC B and QML Q & V
– Monitoring Heavy Ions Latch-up Immunity and Total Dose Capability Better than
100 Krads.
Description
The Atmel ATC18RHA is fabricated on a proprietary 0.18 µm, up to six-layer-metal
CMOS process intended for use with a supply voltage of 1.8V ± 0.15V. Table 1 shows
the range for that Atmel library cells have been characterized.
Table 1. Recommended Operating Conditions
Symbol Parameter
Conditions
Min Typ Max Unit
VDD
VDD3.3
VI
VO
TEMP
DC Supply Voltage Core and Standard I/Os 1.65 1.8 1.95
DC Supply Voltage 3V Interface I/Os
3 3.3 3.6
DC Input Voltage
DC Output Voltage
Operating Free Air
Temperature Range
Military
0 VDD
0 VDD
-55 +125
V
V
V
V
°C
The Atmel cell libraries and megacell compilers have been designed in order to be
compatible with each other. Simulation representations exist for three types of operat-
ing conditions. They correspond to three characterization conditions defined as
follows:
• MIN conditions:
– TJ = -55°C
– VDD (cell) = 1.95V
– Process = fast
• TYP conditions:
– TJ = +25°C
– VDD (cell) = 1.8V
– Process = typ
• MAX conditions:
– TJ = +125°C
– VDD (cell) = 1.65V
– Process = slow
Rad. Hard
0.18 µm CMOS
Cell-based ASIC
for Space Use
ATC18RHA
Advance
Information
Rev. 4261A–AERO–07/03
1
Delays to tri-state are defined as delay to turn off (VGS < VT) of the driving devices.
Output pad drain current corresponds to the output current of the pad when the output
voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to access
resistors (in and out of the die) are taken into account. In order to have accurate timing
estimates, all characterization has been run on electrical netlists extracted from the lay-
out database.
Standard Cell Library
SClib
The Atmel Standard Cell Library, SClib, contains a comprehensive set of a combination
of logic and storage cells. The SClib library includes cells that belong to the following
categories:
• Buffers and Gates
• Multiplexers
• Standard and SEU Hardened Flip-flops
• Standard and SEU Hardened Scan Flip-flops
• Latches
• Adders and Subtractors
Decoding the Cell Name
Table 2 shows the naming conventions for the cells in the SClib library. Each cell name
begins with either a two-, three-, or four-letter code that defines the type of cell. This
indicates the range of standard cells available.
Table 2. Cell Codes
Code
Description
AD Adder
AH Half Adder
AS Adder/Subtractor
AN AND Gate
AOI AND-OR-Invert Gate
AON
AND-OR-AND-Invert Gates
AOR
AND-OR Gate
BUFB
Balanced Buffer
BUFF
Non-Inverting Buffer
BUFT
Non-Inverting Tri-state Buffer
CG Carry Generator
CLK2
Clock Buffer
DF D Flip-flop
DLA Dual Input Latches
H... SEU Hardened Versions
INV0
Inverter
Code
INVB
INVT
LA
MI
MX
ND
NR
OAI
OAN
OR
ORA
SD
SRLA
SU
XN
XR
Description
Balanced Inverter
Inverting Tri-state Buffer
D Latch
Inverting Multiplexer
Multiplexer
NAND Gate
NOR Gate
OR-AND-Invert Gate
OR-AND-OR-Invert Gates
OR Gate
OR-AND Gate
Multiplexed Scan D Flip-flop
Set/Reset Latches with NAND input
Subtractor
Exclusive NOR Gate
Exclusive OR Gate
2 ATC18RHA
4261A–AERO–07/03
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제조업체: ATMEL Corporation
( atmel )
ATC18RHA cmos
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