K4F660412D 반도체 회로 부품 판매점
16M x 4bit CMOS Dynamic RAM with Fast Page Mode
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 Samsung |
K4F660412D,K4F640412D
CMOS DRAM
16M x 4bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power)
are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.
Furthermore, Self-refresh operation is available in L-version. This 16Mx4 Fast Page Mode DRAM family is fabricated using Samsung′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- K4F660412D-JC/L(3.3V, 8K Ref., SOJ)
- K4F640412D-JC/L(3.3V, 4K Ref., SOJ)
- K4F660412D-TC/L(3.3V, 8K Ref., TSOP)
- K4F640412D-TC/L(3.3V, 4K Ref., TSOP)
• Active Power Dissipation
Speed
-45
-50
-60
8K
324
288
252
Unit : mW
4K
432
396
360
• Refresh Cycles
Part
NO.
K4F660412D*
K4F640412D
Refresh
cycle
8K
4K
Refresh time
Normal L-ver
64ms 128ms
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
• Performance Range
Speed tRAC
tCAC
-45 45ns 12ns
-50 50ns 13ns
-60 60ns 15ns
tRC
80ns
90ns
110ns
tPC
31ns
35ns
40ns
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V±0.3V power supply
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
Refresh Timer
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
A0~A10
(A0~A11)*1
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
Row Decoder
Memory Array
16,777,216 x 4
Cells
Column Decoder
Data in
Buffer
Data out
Buffer
DQ0
to
DQ3
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
K4F660412D,K4F640412D
CMOS DRAM
PIN CONFIGURATION (Top Views)
• K4F660412D-J
• K4F640412D-J
VCC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VSS
31 DQ3
30 DQ2
29 N.C
28 N.C
27 N.C
26 CAS
25 OE
24 A12(N.C)*
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 VSS
(J : 400mil SOJ)
• K4F660412D-T
• K4F640412D-T
VCC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VSS
31 DQ3
30 DQ2
29 N.C
28 N.C
27 N.C
26 CAS
25 OE
24 A12(N.C)*
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 VSS
(T : 400mil TSOP(II))
* (N.C) : N.C for 4K Refresh product
Pin Name
A0 - A12
A0 - A11
DQ0 - 3
VSS
RAS
CAS
W
OE
VCC
N.C
Pin Function
Address Inputs(8K Product)
Address Inputs(4K Product)
Data In/Out
Ground
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power(+3.3V)
No Connection
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제조업체: Samsung
( samsung )
K4F660412D cmos
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