IDT54FCT273CEB 반도체 회로 부품 판매점
FAST CMOS OCTAL FLIP-FLOP WITH MASTER RESET
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 Integrated Device Technology |
®
Integrated Device Technology, Inc.
FAST CMOS
OCTAL FLIP-FLOP
WITH MASTER RESET
IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
FEATURES:
• IDT54/74FCT273 equivalent to FAST™ speed;
• IDT54/74FCT273A 45% faster than FAST
• IDT54/74FCT273C 55% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5µA max.)
• Octal D flip-flop with Master Reset
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT273/A/C are octal D flip-flops built using
an advanced dual metal CMOS technology. The IDT54/
74FCT273/A/C have eight edge-triggered D-type flip-flops
MRwith individual D inputs and O outputs. The common buffered
Clock (CP) and Master Reset ( ) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.
All outputs will be forced LOW independently of Clock or
MRData inputs by a LOW voltage level on the input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
CP
DQ
CP
RD
DQ
CP
RD
MR
O0 O1
PIN CONFIGURATIONS
DQ
CP
RD
O2
DQ
CP
RD
O3
DQ
CP
RD
O4
DQ
CP
RD
O5
DQ
CP
RD
O6
DQ
CP
RD
O7
2558 drw 01
MR
O0
D0
D1
O1
O2
D2
D3
O3
GND
1 20
2 19
3 18
4 P20-1 17
5
D20-1
SO20-2
16
6 & 15
7 E20-1 14
8 13
9 12
10 11
Vcc
O7
D7
D6
O6
O5
D5
D4
O4
CP
DIP/SOIC/CERPACK
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.10
INDEX
3 2 20 19
D1 4
1 18 D7
O1 5
17 D6
O2 6 L20-2 16 O6
D2 7
15 O5
D3 8
14 D5
9 10 11 12 13
LCC
TOP VIEW
2558 drw 02
MAY 1992
DSC-4609/2
1
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
Description
DN Data Input
MR Master Reset (Active LOW)
CP Clock Pulse Input (Active Rising Edge)
ON Data Outputs
2558 tbl 05
FUNCTION TABLE
Operating Mode
Reset (Clear)
Load “1”
Load “0”
MR
L
H
H
Inputs
CP
X
↑
↑
DN
X
h
l
Outputs
ON
L
H
L
NOTES:
2558 tbl 06
H = HIGH voltage level steady-state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t care
↑ = LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
to GND
VTERM(3) Terminal Voltage
with Respect
to GND
Commercial Military Unit
–0.5 to +7.0 –0.5 to +7.0 V
–0.5 to VCC –0.5 to VCC V
TA Operating
Temperature
0 to +70 –55 to +125 °C
TBIAS
Temperature
Under Bias
–55 to +125 –65 to +135 °C
TSTG
Storage
Temperature
–55 to +125 –65 to +150 °C
PT Power Dissipation 0.5
0.5 W
IOUT
DC Output Current
120
120 mA
NOTES:
2558 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V
COUT Output Capacitance VOUT = 0V
6
8
10 pF
12 pF
NOTE:
2558 tbl 02
1. This parameter is guaranteed by characterization data and not tested.
7.10 2
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IDT54FCT273CE
FAST CMOS OCTAL FLIP-FLOP WITH MASTER RESET - Integrated Device Technology
IDT54FCT273CEB
FAST CMOS OCTAL FLIP-FLOP WITH MASTER RESET - Integrated Device Technology