CXL5507P 반도체 회로 부품 판매점
CMOS-CCD 1H Delay Line for NTSC
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 Sony Corporation |
CXL5507M/P
CMOS-CCD 1H Delay Line for NTSC
Description
The CXL5507M/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
Features
• Single 5V power supply
• Low power consumption 50mW (Typ.)
• Built-in peripheral circuits
Functions
• 453-bit CCD register
• Clock driver
• Auto-bias circuit
• Input clamp circuit
• Sample-and-hold circuit
Structure
CMOS-CCD
Blook Diagram and Pin Configuration (Top View)
CXL5507M
8 pin SOP (Plastic)
CXL5507P
8 pin DIP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
• Operating temperature Topr –10 to +60
• Storage temperature Tstg –55 to +150
• Allowable power dissipation
PD
CXL5507M 350
CXL5507P 480
V
°C
°C
mW
mW
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5% V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0 Vp-p
(0.5Vp-p typ.)
• Clock frequency
fCLK 7.159090 MHz
• Input clock waveform Sine wave
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 527mVp-p (Max.)
(at internal clamp condition)
876 5
Auto-bias circuit
Bias circuit
CCD
(453bit)
Clamp circuit
1
Output circuit
(S/H 1bit)
23
Timing circuit
Clock driver
Bias circuit (A)
Bias circuit (B)
4
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E90908A7X-PS
CXL5507M/P
Pin Description
Pin No. Symbol
1 IN
2 VGB
3 OUT
4 VSS
5 CLK
6 VGA
7 VDD
8 AB
I/O Description
I Signal input
I Gate control B
O Signal output
— GND
I Clock input
O Gate control A
— Power supply (5V)
O Auto-bias DC output
Impedance
> 10kΩ at no clamp
40 to 500Ω
> 100kΩ
600 to 200kΩ
Description of I/O Signals
Input signals are low level clamped and output signals are
inverted in relation to the input signals. Also, the clamp
condition of input signals are controlled by VGB (Pin 2)
conditions.
0V ........ Internal clamp condition
5V ........ Non internal clamp condition
Center biased to approx. 2.1V by means of
the IC internal resistance (approx. 10kΩ).
In this mode, the input signal is limited to
APL 50% and the maximum input signal
amplitude is 200mVp-p.
Clamp
level
Input waveform
Output waveform
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 7.159090MHz, VCLK = 500mVp-p, sine wave)
See "Electrical Characteristics Test Circuit"
Item
Symbol Test condition
SW condition
Bias
condition Min. Typ. Max. Unit Note
1 2 3 4 5 V1 (V)
Supply current IDD
— a a ba—
5 10 15 mA 1
Low frequency
gain
GL
200kHz,
500mVp-p, sine wave
a
a
b
a
b
–2 0 2 dB 2
Frequency
response
fg
200kHz ←→ 2MHz, b
150mVp-p, sine wave c
a
a
b
b
2.1
–2 –1 0 dB 3
S/H pulse
coupling
CP No signal input
— b a b a 2.1
— — 350 mVp-p 4
S/N ratio
SN No signal input
—b ab c
54 56 — dB 5
Linearity
LIS 5-staircase wave
LIL (For luminance
LIC signals only)
b a ba a
b a ba a
b a ba a
—
37 40 43
18 20 22 %
56 60 64
6
–2–
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CXL5507P cmos
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국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈
( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )
전력반도체 문의 : 010-3582-2743
관련 데이터시트
CXL5507M
CMOS-CCD 1H Delay Line for NTSC - Sony Corporation
CXL5507P
CMOS-CCD 1H Delay Line for NTSC - Sony Corporation