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AM27C010-120DI5 반도체 회로 부품 판매점

1 Megabit (128 K x 8-Bit) CMOS EPROM



Advanced Micro Devices 로고
Advanced Micro Devices
AM27C010-120DI5 데이터시트, 핀배열, 회로
FINAL
Am27C010
1 Megabit (128 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time
— Speed options as fast as 45 ns
s Low power consumption
— 20 µA typical CMOS standby current
s JEDEC-approved pinout
s Single +5 V power supply
s ±10% power supply tolerance standard
s 100% Flashrite™ programming
— Typical programming time of 16 seconds
s Latch-up protected to 100 mA from –1 V to
VCC + 1 V
s High noise immunity
s Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
s Standard 28-pin DIP, PDIP, and 32-pin PLCC
packages
GENERAL DESCRIPTION
The Am27C010 is a 1 Megabit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 128K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast
single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.
Data can be typically accessed in less than 45 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 100 mW in active mode,
and 100 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), re-
sulting in a typical programming time of 16 seconds.
BLOCK DIAGRAM
OE#
CE#
PGM#
A0–A16
Address
Inputs
VCC
VSS
VPP
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
Data Outputs
DQ0–DQ7
Output
Buffers
Y
Gating
1,048,576
Bit Cell
Matrix
10205G-1
Publication# 10205 Rev: G Amendment/0
Issue Date: May 1998


AM27C010-120DI5 데이터시트, 핀배열, 회로
PRODUCT SELECTOR GUIDE
Family Part Number
Am27C010
VCC = 5.0 V ± 5%
Speed Options
-45
-255
VCC = 5.0 V ± 10% -45
-55
-70
-90
-120
-150
-200
Max Access Time (ns)
45 55 70 90 120 150 200 250
CE# (E#) Access (ns)
45 55 70 90 120 150 200 250
OE# (G#) Access (ns)
25 35 35 40 50 65 75 75
CONNECTION DIAGRAMS
Top View
DIP
PLCC
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 PGM# (P#)
30 NC
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE# (G#)
23 A10
22 CE# (E#)
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
10205G-2
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
A14
A13
A8
A9
A11
OE# (G#)
A10
CE# (E#)
DQ7
10205G-3
Notes:
1. JEDEC nomenclature is in parenthesis.
2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.
PIN DESIGNATIONS
A0–A16 = Address Inputs
CE# (E#) = Chip Enable Input
DQ0–DQ7 = Data Input/Outputs
OE# (G#) = Output Enable Input
PGM# (P#) = Program Enable Input
VCC = VCC Supply Voltage
VPP = Program Voltage Input
VSS = Ground
LOGIC SYMBOL
17
A0–A16
DQ0–DQ7
CE# (E#)
PGM# (P#)
OE# (G#)
8
10205G-4
2 Am27C010




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