Am29DL400BT-70FC 판매점 - 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only/ Simultaneous Operation Flash Memory

Am29DL400BT-70FC 반도체 회로 부품 판매점

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only/ Simultaneous Operation Flash Memory

Advanced Micro Devices

PRELIMINARY

Am29DL400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

s Simultaneous Read/Write operations

— Host system can program or erase in one bank,

then immediately and simultaneously read from

the other bank

— Zero latency between read and write operations

— Read-while-erase

— Read-while-program

s Single power supply operation

— 2.7 to 3.6 volt read and write operations for

battery-powered applications

s Manufactured on 0.35 µm process technology

s High performance

— Access times as fast as 70 ns

s Low current consumption (typical values

at 5 MHz)

— 7 mA active read current

— 21 mA active read-while-program or read-while-

erase current

— 17 mA active program-while-erase-suspended

current

— 200 nA in standby mode

— 200 nA in automatic sleep mode

— Standard tCE chip enable access time applies to

transition from automatic sleep mode to active

mode

s Flexible sector architecture

— Two 16 Kword, two 8 Kword, four 4 Kword, and

six 32 Kword sectors in word mode

— Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and

six 64 Kbyte sectors in byte mode

— Any combination of sectors can be erased

— Supports full chip erase

s Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command sequences

s Sector protection

— Hardware method of locking a sector to prevent

any program or erase operation within that

sector

— Sectors can be locked in-system or via

programming equipment

— Temporary Sector Unprotect feature allows code

changes in previously locked sectors

s Top or bottom boot block configurations

available

s Embedded Algorithms

— Embedded Erase algorithm automatically

pre-programs and erases sectors or entire chip

— Embedded Program algorithm automatically

programs and verifies data at specified address

s Minimum 1 million program/erase cycles

guaranteed per sector

s Package options

— 44-pin SO

— 48-pin TSOP

s Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

— Superior inadvertent write protection

s Data# Polling and Toggle Bits

— Provides a software method of detecting

program or erase cycle completion

s Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or

erase cycle completion

s Erase Suspend/Erase Resume

— Suspends or resumes erasing sectors to allow

reading and programming in other sectors

— No need to suspend if sector is in the other bank

s Hardware reset pin (RESET#)

— Hardware method of resetting the device to

reading array data

Publication# 21606 Rev: C Amendment/0

Issue Date: April 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29DL400B is an 4 Mbit, 3.0 volt-only flash

memory device, organized as 262,144 words or

524,288 bytes. The device is offered in 44-pin SO and

48-pin TSOP packages. The word-wide (x16) data ap-

pears on DQ0–DQ15; the byte-wide (x8) data appears

on DQ0–DQ7. This device requires only a single 3.0

volt VCC supply to perform read, program, and erase

operations. A standard EPROM programmer can also

be used to program and erase the device.

The standard device offers access times of 70, 80, 90,

and 120 ns, allowing high-speed microprocessors to

operate without wait states. Standard control pins—

chip enable (CE#), write enable (WE#), and output en-

able (OE#)—control read and write operations, and

avoid bus contention issues.

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides si-

multaneous operation by dividing the memory space

into two banks. Bank 1 contains boot/parameter sec-

tors, and Bank 2 consists of larger, code sectors of uni-

form size. The device can improve overall system

performance by allowing a host system to program or

erase in one bank, then immediately and simultane-

ously read from the other bank, with zero latency. This

releases the system from waiting for the completion of

program or erase operations.

Am29DL400B Features

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

machine that controls the erase and programming

circuitry. Write cycles also internally latch addresses

and data needed for the programming and erase

operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the device automatically returns to

reading array data.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector within that bank that is

not selected for erasure. True background erase can

thus be achieved. There is no need to suspend the

erase operation if the read data is in the other bank.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device to reading array data, enabling the sys-

tem microprocessor to read the boot-up firmware from

the Flash memory.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

AMD’s Flash technology combines years of Flash mem-

ory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The

device electrically erases all bits within a sector simulta-

neously via Fowler-Nordheim tunneling. The bytes are

programmed one byte or word at a time using hot elec-

tron injection.

2 Am29DL400B

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Am29DL400BT-70FC cmos

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Am29DL400BT-70FC 반도체 회로 부품 판매점

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only/ Simultaneous Operation Flash Memory

국내 전력반도체 판매점

일반적인 전자부품 판매점

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