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AT49BV4096-20TI 반도체 회로 부품 판매점

4-Megabit 256K x 16 3-volt Only CMOS Flash Memory



ATMEL Corporation 로고
ATMEL Corporation
AT49BV4096-20TI 데이터시트, 핀배열, 회로
Features
Low Voltage Operation
- 2.7V Read
- 5V Program/Erase
Fast Read Access Time - 120 ns
Internal Erase/Program Control
•• Sector Architecture
- One 8K Words (16K bytes) Boot Block with Programming Lockout
- Two 8K Words (16K bytes) Parameter Blocks
- One 232K Words (464K bytes) Main Memory Array Block
Fast Sector Erase Time - 10 seconds
•• Word-By-Word Programming - 10 µs/Word
Hardware Data Protection
DATA Polling For End Of Program Detection
•• Low Power Dissipation
- 25 mA Active Current
- 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49BV4096 and AT49LV4096 are 3-volt, 4-megabit Flash Memories organized
as 256K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile
CMOS technology, the devices offer access times to 120 ns with power dissipation of
just 67 mW at 2.7V read. When deselected, the CMOS standby current is less than
50 µA.
To allow for simple in-system reprogrammability, the AT49BV4096/LV4096 does not
require high input voltages for programming. Reading data out of the device is similar
to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus
Pin Configurations
(continued)
Pin Name
A0 - A17
CE
OE
WE
RESET
VPP
I/O0 - I/O15
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Program/Erase
Power Supply
Data
Inputs/Outputs
No Connect
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
WE NC
RESET
VPP NC
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
14 13
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
VCC I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
SOIC (SOP)
VPP
NC
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RESET
43 WE
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 NC
32 GND
31 I/O15
30 I/O7
29 I/O14
28 I/O6
27 I/O13
26 I/O5
25 I/O12
24 I/O4
23 VCC
4-Megabit
(256K x 16)
3-volt Only
CMOS Flash
Memory
AT49BV4096
AT49LV4096
Preliminary
AT49BV4096/LV4096
0874A–5/97


AT49BV4096-20TI 데이터시트, 핀배열, 회로
contention. Reprogramming the AT49BV4096/LV4096 is
performed by first erasing a block of data and then pro-
gramming on a word-by-word basis.
The device is erased by executing the erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into three blocks for erase op-
erations. There are two 8K word parameter block sections
and one sector consisting of the boot block and the main
memory array block. The AT49BV4096/LV4096 is pro-
grammed on a word-by-word basis.
The device has the capability to protect the data in the
boot block; this feature is enabled by a command se-
Block Diagram
quence. Once the boot block programming lockout feature
is enabled, the data in the boot block cannot be changed
when input levels of 3.6 volts or less are used. The typical
number of program and erase cycles is in excess of
10,000 cycles.
The optional 8K word boot block section includes a repro-
gramming lock out feature to provide data integrity. The
boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is protected
from being reprogrammed.
During a chip erase, sector erase, or word programming,
the VPP pin must be at 5V ± 10%.
Device Operation
READ: The AT49BV4096/LV4096 is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the ad-
dress pins is asserted on the outputs. The outputs are put
in the high impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in prevent-
ing bus contention.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode de-
pending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command se-
quences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command
codes). The command sequences are written by applying
a low pulse on the WE or CE input with CE or WE low
(respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data
is latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
2 AT49BV/LV4096
RESET: A RESET input pin is provided to ease some
system applications. When RESET is at a logic high level,
the device is in its standard operating mode. A low level on
the RESET input halts the present device operation and
puts the outputs of the device in a high impedance state.
When a high level is reasserted on the RESET pin, the
device returns to the Read or Standby mode, depending
upon the state of the control inputs. By applying a 12V ±
0.5V input signal to the RESET pin the boot block array
can be reprogrammed even if the boot block program lock-
out feature has been enabled (see Boot Block Program-
ming Lockout Override section).
ERASURE: Before a word can be reprogrammed, it must
be erased. The erased state of memory bits is a logical “1”.
The entire device can be erased by using the Chip Erase
command or individual sectors can be erased by using the
Sector Erase commands.
CHIP ERASE: The entire device can be erased at one
time by using the 6-byte chip erase software code. After
the chip erase has been initiated, the device will internally
time the erase operation so that no external clocks are re-
quired. The maximum time to erease the chip is tEC.




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제조업체: ATMEL Corporation

( atmel )

AT49BV4096-20TI cmos

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AT49BV4096-20TC

4-Megabit 256K x 16 3-volt Only CMOS Flash Memory - ATMEL Corporation



AT49BV4096-20TI

4-Megabit 256K x 16 3-volt Only CMOS Flash Memory - ATMEL Corporation