HYMD512M646BKFS8-H 판매점 - Unbuffered DDR SO-DIMM

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128Mx64 bits

Unbuffered DDR SO-DIMM

HYMD512M646B(L)FS8-J/M/K/H/L

DESCRIPTION

Hynix HYMD512M646B(L)FS8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small

Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 128Mx64 high-speed memory arrays.

Hynix HYMD512M646B(L)FS8-J/M/K/H/L series consists of eight 128Mx8 DDR SDRAM in FBGA packages on a

200pin glass-epoxy substrate. Hynix HYMD512M646B(L)FS8-J/M/K/H/L series provide a high performance 8-byte

interface in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.

Hynix HYMD512M646B(L)FS8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchro-

nous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control

inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on

both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high

bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable

latencies and burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD512M646B(L)FS8-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect

function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix

to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

• 1GB (128M x 64) Unbuffered DDR SO-DIMM based • Data inputs on DQS centers when write (centered

on 128Mx8 DDR MCP SDRAM

DQ)

• 200-pin small outline dual in-line memory module

(SO-DIMM)

• Data strobes synchronized with output data for read

and input data for write

• 2.5V +/- 0.2V VDD and VDDQ Power supply

• Programmable CAS Latency 2 / 2.5 supported

• All inputs and outputs are compatible with SSTL_2

interface

• Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

• Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz/166MHz

• All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

• tRAS Lock-out function supported

• Internal four bank operations with single pulsed RAS

• Auto refresh and self refresh supported

• 8192 refresh cycles / 64ms

• Data(DQ), Data strobes and Write masks latched on

both rising and falling edges of the clock

ORDERING INFORMATION

Part No.

HYMD512M646B(L)FS8-J

HYMD512M646B(L)FS8-M

HYMD512M646B(L)FS8-K

HYMD512M646B(L)FS8-H

HYMD512M646B(L)FS8-L

Power Supply

VDD=2.5V

VDDQ=2.5V

Clock Frequency

166MHz (*DDR333)

133MHz (*DDR266:2-2-2)

133MHz (*DDR266A)

133MHz (*DDR266B)

100MHz (*DDR200)

Interface

Form Factor

SSTL_2

200pin Unbuffered SO-DIMM

67.6mm x 31.75mm x 1mm

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1 / Jan. 2004

HYMD512M646BKFS8-H 반도체 회로 부품 판매점

Unbuffered DDR SO-DIMM

국내 전력반도체 판매점

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