MC100ES6210 반도체 회로 부품 판매점
Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer
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 Freescale Semiconductor |
Freescale Semiconductor
Technical Data
Low Voltage 2.5/3.3 V Differential
ECL/PECL/HSTL Fanout Buffer
MC100ES6210
Rev 3, 02/2005
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MC100ES6210
The MC100ES6210 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6210
supports various applications that require to distribute precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low clock skew outputs and superior digital
signal characteristics. Target applications for this clock driver is high performance
clock distribution in computing, networking and telecommunication systems.
LOW VOLTAGE DUAL
1:5 DIFFERENTIAL PECL/ECL/HSTL
CLOCK FANOUT BUFFER
Features
• Dual 1:5 differential clock distribution
• 30 ps maximum device skew
• Fully differential architecture from input to all outputs
• SiGe technology supports near-zero output skew
• Supports DC to 3 GHz operation of clock or data signals
• ECL/PECL compatible differential clock outputs
• ECL/PECL compatible differential clock inputs
• Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply
• Standard 32 lead LQFP package
• Industrial temperature range
• Pin and function compatible to the MC100EP210
• 32-lead Pb-free Package Available
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Functional Description
The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The
device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical,
differential ECL/PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible signals.
If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6210 can be driven
by single-ended ECL/PECL signals utilizing the VBB bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6210 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6210 supports positive (PECL) and negative (ECL) supplies. The is function and pin compatible to the MC100EP210.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
CLKA
CLKA
VCC
CLKB
CLKB
VCC
QA0
QA0
QA1
QA1
QA2
QA2
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
QB2
QB2
QB3
QB3
QB4
QB4
VBB
Figure 1. MC100ES6210 Logic Diagram
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24 23 22 21 20 19 18 17
VCC 25
16 VCC
Q2 26
15 QB2
Q2 27
14 QB2
Q1 28
Q1 29
MC100ES6210
13 QB3
12 QB3
Q0 30
11 QB4
Q0 31
10 QB4
VCC 32
9 VCC
12345678
Figure 2. 32-Lead Package Pinout (Top View)
Table 1. Pin Configuration
Pin
CLKA, CLKA
CLKB, CLKB
QA[0-4], QA[0-4]
QB[0-4], QB[0-4]
VEE(1)
VCC
I/O
Input
Input
Output
Output
Supply
Supply
Type
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
Function
Differential reference clock signal input (fanout buffer A)
Differential reference clock signal input (fanout buffer B)
Differential clock outputs (fanout buffer A)
Differential clock outputs (fanout buffer B)
Negative power supply
Positive power supply. All VCC pins must be connected to the positive
power supply for correct DC and AC operation.
VBB
Output
DC
Reference voltage output for single ended ECL or PECL operation
1. In ECL mode (negative power supply mode), VEE is either –3.3 V or –2.5 V and VCC is connected to GND (0 V). In PECL mode (positive
power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are
referenced to the most positive supply (VCC)
Table 2. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min Max Unit Condition
VCC
VIN
VOUT
IIN
IOUT
TS
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
–0.3
–0.3
–0.3
–65
3.6
VCC + 0.3
VCC + 0.3
±20
±50
125
V
V
V
mA
mA
°C
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
MC100ES6210
2
Advanced Clock Drivers Devices
Freescale Semiconductor
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MC100ES6210 buffer
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MC100ES6210
Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer - Freescale Semiconductor
