HD74LV2G126A 반도체 회로 부품 판매점
Dual Bus Buffer
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 Renesas Technology |
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HD74LV2G126A
Dual Bus Buffer with 3–state Output
REJ03D0100–0500Z
(Previous ADE-205-348D (Z))
Rev.5.00
Sep.30.2003
Description
The HD74LV2G126A has dual bus buffer with 3–state output in a 8 pin package. Output is disabled when
the associated output enable (OE) input is low. To ensure the high impedance state during power up or
power down, OE should be connected to VCC through a pull-down resistor; the minimum value of the
resistor is determined by the current souring capability of the driver. Low voltage and high-speed operation
is suitable for the battery powered products (e.g., notebook computers), and the low power consumption
extends the battery life.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• Electrical characteristics equivalent to the HD74LV126A
Supply voltage range : 1.65 to 5.5 V
Operating temperature range : –40 to +85°C
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
• All the logical input has hysteresis voltage for the slow transition.
• Ordering Information
Part Name
Package Type
Package Code Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV2G126AUSE SSOP-8 pin
TTP-8DBV
US
E (3,000 pcs/reel)
Rev.5.00, Sep.30.2003, page 1 of 9
www.DataSheet4U.com
HD74LV2G126A
Outline and Article Indication
• HD74LV2G126A
Index band
Lot No.
SSOP-8
Function Table
Inputs
OE
H
H
L
H : High level
L : Low level
X : Immaterial
Z : High impedance
A
H
L
X
YMW
L26
Y : Year code
(the last digit of year)
M : Month code
W : Week code
Marking
Output Y
H
L
Z
Rev.5.00, Sep.30.2003, page 2 of 9
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HD74LV2G126A buffer
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