|
ON Semiconductor |
MC74LCX240
Low−Voltage CMOS
Octal Buffer
With 5 V−Tolerant Inputs and Outputs
(3−State, Inverting)
The MC74LCX240 is a high performance, inverting octal buffer
operating from a 2.3 to 3.6 V supply. High impedance TTL compatible
inputs significantly reduce current loading to input drivers while TTL
compatible outputs offer improved switching noise performance. A VI
specification of 5.5 V allows MC74LCX240 inputs to be safely driven
from 5 V devices. The MC74LCX240 is suitable for memory address
driving and all TTL level bus oriented transceiver applications.
Current drive capability is 24 mA at the outputs. The Output Enable
(OE) input, when HIGH, disables the outputs by placing them in a
HIGH Z condition.
Features
• Designed for 2.3 to 3.6 V VCC Operation
• 5 V Tolerant − Interface Capability With 5 V TTL Logic
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0 V
• LVTTL Compatible
• LVCMOS Compatible
www.DataSheet4U.com
• 24 mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500 mA
• ESD Performance: Human Body Model >2000 V
Machine Model >200 V
• Pb−Free Packages are Available*
http://onsemi.com
MARKING
DIAGRAMS
20
1
20
SOIC−20
DW SUFFIX
CASE 751D
1
LCX240
AWLYYWWG
20
1
20
TSSOP−20
DT SUFFIX
CASE 948E
1
LCX
240
ALYWG
G
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 7
1
Publication Order Number:
MC74LCX240/D
MC74LCX240
VCC 2OE 1O0 2D0 1O1 2D1 1O2 2D2 1O3 2D3
20 19 18 17 16 15 14 13 12 11
1
1OE
2
1D0
4
1D1
18
1O0
16
1O1
1 2 3 4 5 6 7 8 9 10
1OE 1D0 2O0 1D1 2O1 1D2 2O2 1D3 2O3 GND
Figure 1. Pinout: 20−Lead (Top View)
6
1D2
8
1D3
14
1O2
12
1O3
19
2OE
PIN NAMES
Pins
Function
nOE
1Dn, 2Dn
1On, 2On
Output Enable Inputs
Data Inputs
3−State Outputs
17
2D0
15
2D1
13
2D2
11
2D3
3
2O0
5
2O1
7
2O2
9
2O3
Figure 2. LOGIC DIAGRAM
TRUTH TABLE
INPUTS
1OE
2OE
1Dn
2Dn
OUTPUTS
1On, 2On
LL
H
LH
HX
L
Z
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
X = High or Low Voltage Level and Transitions Are Acceptable; for ICC reasons, DO NOT FLOAT Inputs
http://onsemi.com
2
|