W152 판매점 - Spread Aware/ Eight Output Zero Delay Buffer

W152 반도체 회로 부품 판매점

Spread Aware/ Eight Output Zero Delay Buffer

Cypress Semiconductor

W152

Spread Aware™, Eight Output Zero Delay Buffer

Features

• Spread Aware™—designed to work with SSFTG

reference signals

• Two banks of four outputs each

• Configuration options to halve, double, or quadruple

the reference frequency refer to Table 1 to determine

the specific option which meets your multiplication

needs

• Outputs may be three-stated

• Available in 16-pin SOIC package

• Extra strength output drive available (-11/-12 versions)

• Contact factory for availability information on 16-pin

TSSOP

Key Specifications

Operating Voltage: ............................................... 3.3V±10%

Operating Range: .................... 15 MHz < fOUTQA < 140 MHz

Cycle-to-Cycle Jitter: (Refer to Figure 3) .................... 225 ps

Cycle-to-Cycle Jitter: Frequency Range

25 to140 MHz ......................................................... 125 ps

Output to Output Skew: Between Banks ..................... 215 ps

Output to Output Skew: Within Banks

(Refer to Figure 4) ...................................................100 ps

Total Timing Budget Impact: ........................................ 555 ps

Max. Phase Error Variation: ......................................±225 ps

Tracking Skew:...........................................................±130 ps

Table 1. Configuration Options

Device

W152-1/11[1]

W152-2/12[2]

Feedback Signal

QA0:3 or QB0:3

QA0:3

QB0:3

QA0:3

REFx1

REFx2

W152-3

QA0:3

REFx2

W152-3

QB0:3

REFx4

W152-4

QA0:3 or QB0:3 REFx2

Notes:

1. W152-11 has stronger output drive than the W152-1.

2. W152-12 has stronger output drive than the W152-2.

QB0:3

REFx1

REF/2

REFx1

REFx2

Block Diagram

Pin Configuration

FBIN

REF

(present on the -3 and -4 only)

÷2

PLL

MUX

SEL0

SEL1

÷2

(present on the -2, -12, and -3 only)

QA0

QA1

QA2

QA3

QB0

QB1

QB2

QB3

REF

QA0

QA1

VDD

GND

QB0

QB1

SEL1

16 FBIN

15 QA3

14 QA2

13 VDD

12 GND

11 QB3

10 QB2

9 SEL0

Spread Aware is a trademark of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

June 14, 2000, rev. *B

W152

Pin Definitions

Pin Name

REF

Pin No.

FBIN

QA0:3

QB0:3

VDD

GND

SEL0:1

2, 3, 14, 15

6, 7, 10, 11

4, 13

5, 12

9, 8

Type

Pin Description

Reference Input: The output signals QA0:3 through QB0:3 will be synchronized to

this signal unless the device is programmed to bypass the PLL.

Feedback Input: When programmed to zero delay buffer mode, this input must be

fed by one of the outputs (QA0:3 or QB0:3) to ensure proper functionality. If the trace

between FBIN and the output pin being used for feedback is equal in length to the

traces between the outputs and the signal destinations, then the signals received at

the destinations will be synchronized to the REF signal input.

Outputs from Bank A: The frequency of the signals provided by these pins is deter-

mined by the feedback signal connected to FBIN, and the specific W152 option being

used. See Table 2.

Outputs from Bank B: The frequency of the signals provided by these pins is deter-

mined by the feedback signal connected to FBIN, and the specific W152 option being

used. See Table 2.

Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for

optimal jitter performance.

Ground Connections: Connect all grounds to the common system ground plane.

Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per

Table 2.

Overview

Functional Description

The W152 products are eight-output zero delay buffers. A

Phase-Locked Loop (PLL) is used to take a time-varying signal

and provide eight copies of that same signal out. The external

feedback to the PLL provides outputs in phase with the refer-

ence inputs.

Internal dividers exist in some options allowing the user to get

a simple multiple (/2, x2, x4) of the reference input, for details

see Table 1. Because the outputs are separated into two

banks, it is possible to provide some combination of these mul-

tiples at the same time.

Spread Aware

Many systems being designed now utilize a technology called

Spread Spectrum Frequency Timing Generation. Cypress has

been one of the pioneers of SSFTG development, and we de-

signed this product so as not to filter off the Spread Spectrum

feature of the Reference input, assuming it exists. When a zero

delay buffer is not designed to pass the SS feature through,

the result is a significant amount of tracking skew which may

cause problems in systems requiring synchronization.

For more details on Spread Spectrum timing technology,

please see the Cypress application note titled, “EMI Suppres-

sion Techniques with Spread Spectrum Frequency Timing

Generator (SSFTG) ICs.”

Logic inputs provide the user the ability to turn off one or both

banks of clocks when not in use, as described in Table 2. Dis-

abling a bank of unused outputs will reduce jitter and power

consumption, and will also reduce the amount of EMI generat-

ed by the W152.

These same inputs allow the user to bypass the PLL entirely if

so desired. When this is done, the device no longer acts as a

zero delay buffer, it simply reverts to a standard eight-output

clock driver.

The W152 PLL enters an auto power-down mode when there

are no rising edges on the REF input. In this mode, all outputs

are three-stated and the PLL is turned off.

Table 2. Input Logic

SEL1 SEL0 QA0:3

QB0:3

PLL

0 0 Three-State Three-State Shutdown

0 1 Active Three-State Active, Utilized

1 0 Active

Active

Shutdown,

Bypassed

1 1 Active

Active Active, Utilized

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W152 buffer

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W152 반도체 회로 부품 판매점

Spread Aware/ Eight Output Zero Delay Buffer

국내 전력반도체 판매점

일반적인 전자부품 판매점

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