8V79S674 반도체 회로 부품 판매점
LVPECL Clock Divider and Fanout Buffer
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 IDT |
Differential-to-3.3V, 2.5V LVPECL
Clock Divider and Fanout Buffer
8V79S674
DATA SHEET
General Description
The 8V79S674 is a clock divider and fanout buffer. The device has
been designed for clock signal division in wireless base station radio
equipment boards. The device is optimized to deliver excellent
additive phase jitter performance. The 8V79S674 uses SiGe
technology for an optimum of high clock frequency and low phase
noise performance, combined with high power supply noise rejection.
The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four
low-skew LVPECL outputs are available and support clock output
frequencies up to 2500MHz (÷1 frequency division). Outputs can be
disabled to save power consumption if not used. The device is
packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
• Clock signal division and distribution
• SiGe technology for high-frequency and fast signal rise/fall times
• Four low-skew LVPECL clock outputs
• Supports frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum frequency: 2500MHz
• Maximum output skew: 50ps (maximum)
• Maximum LVPECL output rise/fall time: 200ps (maximum)
• 3.3V or 2.5V core and output supply mode
• Supports 1.8V I/O logic levels for all control pins
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
IN ÷N
nIN
2x 50
VT
VREFAC
Reference Voltage
N[1:0]
nOEA
nOEB
Pulldown
Pulldown
Pulldown
.
8V79S674 REVISION 2 04/10/15
Pin Assignment
Q0
nQ0
Q1
nQ1
15 14 13 12 11
VCC 16
10 Q3
Q0 17
9 nQ3
Q2
nQ2
Q3
nQ3
nQ0 18
nOEA 19
VEE 20
1
8V79S674
8 nOEB
7 N1
6 VEE
2 3 45
20-pin, 4mm x 4mm VFQFN Package
1 ©2015 Integrated Device Technology, Inc.
8V79S674 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5, 7
6, 20
8
9, 10
11, 16
12, 13
14, 15
17, 18
19
—
Name
nIN
VREFAC
VT
IN
N0, N1
VEE
nOEB
nQ3, Q3
VCC
Q2, nQ2
Q1, nQ1
Q0, nQ0
nOEA
VEE_EP
Type
Input
Output
Input
Input
Power
Input
Output
Power
Output
Output
Output
Input
Power
Pulldown
Pulldown
Pulldown
Description
Inverting differential clock signal input. Internal termination 50 to VT.
Reference voltage for AC-coupled applications of IN, nIN.
Leave open if IN, nIN is used with LVDS signals. Connect 50 to VEE if IN,
nIN is used with LVPECL signals.
Non-inverting differential clock signal input. Internal termination 50 to VT.
Frequency divider controls. 1.8V LVCMOS/LVTTL interface levels.
Negative power supply voltage (ground).
Output enable control for the Q1, Q2 and Q3 outputs. 1.8V
LVCMOS/LVTTL interface levels.
Differential clock output pair. LVPECL output levels.
Power supply voltage.
Differential clock output pair. LVPECL output levels
Differential clock output pair. LVPECL output levels
Differential clock output pair. LVPECL output levels
Output enable control for the Q0 output. 1.8V LVCMOS/LVTTL interface
levels.
Exposed package pad negative supply voltage (ground). Return current
path for the Q0, Q1, Q2 and Q3 outputs. This pin must be connected to
ground.
NOTE: Pulldown refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
Maximum
Units
pF
k
DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER
2
REVISION 2 04/10/15
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8V79S674 buffer
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