IDT8T79S818I-08 반도체 회로 부품 판매점
1-to-8 Differential to Universal Output Clock Divider/Fanout Buffer
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 Integrated Device Technology |
1-to-8 Differential to Universal Output
Clock Divider/Fanout Buffer
IDT8T79S818I-08
DATASHEET
General Description
The IDT8T79S818I-08 is a high performance, 1-to-8, differential input
to universal output clock divider and fanout buffer. The device is
designed for frequency-division and signal fanout of high-frequency
clock signals in applications requiring four different output
frequencies generated simultaneously. Each bank of two outputs has
a selectable divider value of ÷1 through ÷6 and ÷8. The
IDT8T79S818I-08 is optimized for 3.3V and 2.5V supply voltages and
a temperature range of -40°C to 85°C. The device is packaged in a
space-saving 32 lead VFQFN package.
Features
• Four banks of two low skew outputs
• Selectable bank output divider values: ÷1 through ÷6 and ÷8
• One differential PCLK, nPCLK input
• PCLK, nPCLK input pair can accept the following differential input
levels: LVPECL, LVDS levels
• Maximum input frequency: 1.5GHz
• LVCMOS control inputs
• QXx ÷1 edge aligned to QXx ÷n edge
• Individual output divider control via serial interface
• Individual output enable/disable control via serial interface
• Individual output type control, LVDS or LVPECL, via serial
interface
• 2.375V to 3.465V supply voltage operation
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Pin Assignment
Block Diagram
VCC
VCC 25
VEE 26
nQA1 27
QA1 28
nQA0 29
QA0 30
VCC 31
SDATA 32
IDT8T79S818I-08
32 lead VFQFN
5mm x 5mm x 0.925mm
Pad size 3.15mm x 3.15mm
NL package
Top View
16 VCC
15 VEE
14 QD0
PCLK Pulldown
nPCLK Pullup/Pulldown
VEE VEE
13 nQD0
12 QD1
11 nQD1
10 VCC
PWR_SEL Pulldown
9 PWR_SEL
VEE
Dividers
RST
7
nRST Pullup
OE Pulldown
LE Pulldown
SCLK Pulldown
SDATA Pulldown
VCC
D ivid e r S e le ct,
Output Type and
O utput Enable
logic
VEE VEE VEE VEE
12
10
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
QC0
nQC0
QC1
nQC1
QD0
nQD0
QD1
nQD1
MISO
IDT8T79S818A-08NLGI REVISION A JULY 11, 2013
1
©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet
1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
SCLK
Input
Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels.
2
MISO
Output
Serial Control Port Mode Data Output. LVCMOS/LVTTL interface levels.
Frequency Divider Reset. When the nRST is released (rising edge), the divided
3
nRST
Input
Pullup
clock outputs are activated and will transition to a high state simultaneously.
See also Timing Diagram. LVCMOS/LVTTL interface levels (“Figure 1. Timing
Diagram”).
4
PCLK
Input
Pulldown Non-inverting differential clock input.
5
nPCLK
Input
Pullup /
Pulldown
Inverting differential clock input. VCC / 2 by default when left floating.
6
OE
Input
Pulldown
Default output disable. LVCMOS/LVTTL interface levels. See “Table 3B. OE
Truth Table”.
7, 10, 16,
25, 31
VCC
Power
Power supply voltage pin.
8
LE
Input
Pulldown
Serial Control Port Mode Load Enable. Latches data when the pin gets a high
level. Outputs are disabled when LE is low. LVCMOS/LVTTL interface levels.
9 PWR_SEL
Pulldown Power supply selection. See “Table 3A. PWR_SEL Truth Table”.
11, 12
nQD1, QD1
Output
Differential output pair Bank D, output 1. LVPECL or LVDS interface levels.
13, 14
nQD0, QD0
Output
Differential output pair Bank D, output 0. LVPECL or LVDS interface levels.
15, 26
17, 18
VEE
nQC1, QC1
Power
Output
Negative power supply pins.
Differential output pair Bank C, output 1. LVPECL or LVDS interface levels.
19, 20
nQC0, QC0
Output
Differential output pair Bank C, output 0. LVPECL or LVDS interface levels.
21, 22
nQB1, QB1
Output
Differential output pair Bank B, output 1. LVPECL or LVDS interface levels.
23, 24
nQB0, QB0
Output
Differential output pair Bank B, output 0. LVPECL or LVDS interface levels.
27, 28
nQA1, QA1
Output
Differential output pair Bank A, output 1. LVPECL or LVDS interface levels.
29, 30
nQA0, QA0
Output
Differential output pair Bank A, output 0. LVPECL or LVDS interface levels.
32
SDATA
Input
Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See “Table 2. Pin Characteristics” for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLUP
RPULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
ROUT
Output Impedance MISO
Test Conditions
VCC = 3.3V
VCC = 2.5V
Minimum
Typical
2
51
51
125
145
Maximum
Units
pF
k
k
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013
2
©2013 Integrated Device Technology, Inc.
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IDT8T79S818I-08 buffer
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1-to-8 Differential to Universal Output Clock Divider/Fanout Buffer - Integrated Device Technology
