AT49BV512-15VI 반도체 회로 부품 판매점
512K 64K x 8 Single 2.7-volt Battery-Voltage Flash Memory
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 ATMEL Corporation |
Features
• Single Supply Voltage, Range 2.7V to 3.6V
• Single Supply for Read and Write
• Fast Read Access Time - 120 ns
• Internal Program Control and Timer
• 8K bytes Boot Block With Lockout
• Fast Erase Cycle Time - 10 seconds
• Byte By Byte Programming - 30 µs/Byte typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
Description
The AT49BV512 is a 3-volt-only, 512K Flash memories organized as 65,536 words of
8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the
devices offer access times to 120 ns with power dissipation of just 90 mW over the
commercial temperature range. When the devices are deselected, the CMOS standby
current is less than 50 µA.
To allow for simple in-system reprogrammability, the AT49BV512 does not require
high input voltages for programming. Three-volt-only commands determine the read
and programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49BV512 is performed by erasing
the entire 1 megabit of memory and then programming on a byte by byte basis. The
(continued)
Pin Configurations
DIP Top View
Pin Name Function
A0 - A15
Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 WE
30 NC
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A11
A9
A8
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
PLCC Top View
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
512K (64K x 8)
Single 2.7-volt
Battery-Voltage™
Flash Memory
AT49BV512
Rev. 1026C–09/98
1
typical byte programming time is a fast 30 µs. The end of a
program cycle can be optionally detected by the DATA poll-
ing feature. Once the end of a byte program cycle has
been detected, a new access for a read or program can
begin. The typical number of program and erase cycles is
in excess of 10,000 cycles.
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
OE, CE AND WE
LOGIC
Y DECODER
X DECODER
DATA INPUTS/OUTPUTS
I/O0 - I/O7
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(56K BYTES)
OPTIONAL BOOT
BLOCK (8K BYTES)
FFFFH
2000H
1FFFH
0000H
Device Operation
READ: The AT49BV512 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention.
ERASURE: Before a byte can be reprogrammed, the 64K
bytes memory array (or 56K bytes if the boot block featured
is used) must be erased. The erased state of the memory
bits is a logical “1”. The entire device can be erased at one
time by using a 6-byte software code. The software chip
erase code consists of 6-byte load commands to specific
address locations with a specific data pattern (please refer
to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle oper-
ation (please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP
cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Com-
mand Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
2 AT49BV512
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제조업체: ATMEL Corporation
( atmel )
AT49BV512-15VI battery
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관련 데이터시트
AT49BV512-15VC
512K 64K x 8 Single 2.7-volt Battery-Voltage Flash Memory - ATMEL Corporation
AT49BV512-15VI
512K 64K x 8 Single 2.7-volt Battery-Voltage Flash Memory - ATMEL Corporation