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ATMEL Corporation |
Features
• Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
• Fast Read Access Time – 70 ns
• Internal Erase/Program Control
• Sector Architecture
– One 8K Word (16K Bytes) Boot Block with Programming Lockout
– Two 4K Word (8K Bytes) Parameter Blocks
– One 112K Word (224K Bytes) Main Memory Array Block
• Fast Sector Erase Time – 10 Seconds
• Byte-by-byte or Word-by-word Programming – 30 µs Typical
• Hardware Data Protection
• Data Polling for End of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
Description
The AT49BV/LV2048A is a 3-volt, 2-megabit Flash memory organized as 262,144
words of 8 bits each or 128K words of 16 bits each. Manufactured with Atmel’s
advanced nonvolatile CMOS technology, the device offers access times to 70 ns with
power dissipation of just 67 mW at 2.7V read. When deselected, the CMOS standby
current is less than 50 µA.
The device contains a user-enabled “boot block” protection feature. The
AT49BV/LV2048A locates the boot block at lowest order addresses (“bottom boot”).
To allow for simple in-system reprogrammability, the AT49BV/LV2048A does not
require high input voltages for programming. Reading data out of the device is similar
to reading from an EPROM; it has standard CE, OE and WE inputs to avoid bus con-
tention. Reprogramming the AT49BV/LV2048A is performed by first erasing a block of
data and then programming on a byte-by-byte or word-by-word basis.
2-megabit
(256K x 8/
128K x 16)
Single 2.7-volt
Battery-Voltage™
Flash Memory
AT49BV2048A
AT49LV2048A
Pin Configurations
Pin Name
A0 - A16
CE
OE
WE
RESET
VPP
I/O0 - I/O15
I/O15(A-1)
BYTE
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
VPP can be left unconnected or connected to VCC, GND, 5V or
12V. The input has no effect on the operation of the device.
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
Rev. 1914D–FLASH–03/02
1
AT49BV/LV2048A SOIC (SOP)
VPP
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RESET
43 WE
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE
32 GND
31 I/O15/A-1
30 I/O7
29 I/O14
28 I/O6
27 I/O13
26 I/O5
25 I/O12
24 I/O4
23 VCC
AT49BV/LV2048A TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
VPP
NC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 A16
47 BYTE
46 GND
45 I/O15/A-1
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 GND
26 CE
25 A0
Note: “•” denotes a white dot on the package.
The device is erased by executing the Erase command sequence; the device internally con-
trols the erase operation. The memory is divided into four blocks for erase operations. There
are two 4K word parameter block sections, the boot block, and the main memory array block.
The typical number of program and erase cycles is in excess of 10,000 cycles.
The 8K word boot block section includes a reprogramming lock out feature to provide data
integrity. This feature is enabled by a command sequence. Once the boot block programming
lockout feature is enabled, the data in the boot block cannot be changed when input levels of
5.5 volts or less are used. The boot sector is designed to contain user secure code.
The BYTE pin controls whether the device data I/O pins operate in the byte or word configura-
tion. If the BYTE pin is set at a logic “1” or left open, the device is in word configuration, I/O0 -
I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins
I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-
stated and the I/O15 pin is used as an input for the LSB (A-1) address function.
2 AT49BV/LV2048A
1914D–FLASH–03/02
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