AT49BV040-12TC 반도체 회로 부품 판매점
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory
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 ATMEL Corporation |
Features
• Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
• Fast Read Access Time - 120 ns
• Internal Program Control and Timer
• 16K bytes Boot Block With Lockout
• Fast Chip Erase Cycle Time - 10 seconds
• Byte-by-Byte Programming - 30 µs/Byte Typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
• Small Packaging
– 8 x 8 mm CBGA
– 8 x 14 mm V-TSOP
Description
The AT49BV/LV040 are 3-volt-only, 4-megabit Flash memories organized as 524,288
words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS tech-
nology, the devices offer access times to 120 ns with power dissipation of just 90 mW
over the commercial temperature range. When the device is deselected, the CMOS
standby current is less than 50 µA.
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49BV/LV040 locates the boot block at lowest order
addresses (“bottom boot”); the AT49BV/LV040T locates it at highest order addresses
(“top boot”).
(continued)
Pin Configurations
Pin Name
A0 - A18
CE
OE
WE
I/O0 - I/O7
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
PLCC Top View
CBGA Top View
1234567
A
GND I/O6 VCC VCC I/O2 OE GND
B
A17 I/O7 I/O4 NC NC I/O0 CE
C
A10 NC I/O5 NC I/O3 I/O1 A0
D
A14 A13 A9 NC NC A6 A3
E
A16 A11 WE NC A7 A4 A1
F
A15 A12 A8 NC A18 A5 A2
V - TSOP Top View (8 x 14 mm) or
T - TSOP Top View (8 x 20 mm)
4-Megabit
(512K x 8)
Single 2.7-volt
Battery-Voltage™
Flash Memory
AT49BV040
AT49BV040T
AT49LV040
AT49LV040T
AT49BV/LV040
0679AX-A–9/97
1
To allow for simple in-system reprogrammability, the
AT49BV/LV040 does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV040 is performed by eras-
ing the entire 4 megabits of memory and then programming
on a byte-by-byte basis. The typical byte programming
time is a fast 30 µs. The end of a program cycle can be
optionally detected by the DATA polling feature. Once the
end of a byte program cycle has been detected, a new
access for a read or program can begin. The typical num-
ber of program and erase cycles is in excess of 10,000
cycles.
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
AT49BV/LV040
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(496K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
7FFFFH
03FFFH
00000H
AT49BV/LV040T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(496K BYTES)
7FFFFH
7C000H
00000H
Device Operation
READ: The AT49BV/LV040 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention.
ERASURE: Before a byte can be reprogrammed, the
512K bytes memory array (or 496K bytes if the boot block
featured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is erased,
the device is programmed (to a logical “0”) on a byte-by-
byte basis. Please note that a data “0” cannot be pro-
grammed back to a “1”; only erase operations can convert
2 AT49BV/LV040
“0”s to “1”s. Programming is accomplished via the internal
device command register and is a 4 bus cycle operation
(please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP
cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
optional to the user. The address range of the
AT49BV/LV040 boot block is 00000H to 03FFFH while the
address range of the AT49BV/LV040T boot block is
7C000H to 7FFFFH.
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제조업체: ATMEL Corporation
( atmel )
AT49BV040-12TC battery
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관련 데이터시트
AT49BV040-12TC
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory - ATMEL Corporation
AT49BV040-12TI
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory - ATMEL Corporation