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Toshiba |
TC75S55F/FU/FE
TOSHIBA CMOS Linear Integrated Circuit Silicon Monolithic
TC75S55F,TC75S55FU,TC75S55FE
Single Operational Amplifier
The TC75S55F/TC75S55FU/TC75S55FE is a CMOS single-
operation amplifier which incorporates a phase compensation
circuit. It is designed for use with a low-voltage, low-current
power supply; this differentiates this device from conventional
general-purpose bipolar op-amps.
Features
• Low-voltage operation : VDD = ±0.9~3.5 V or 1.8~7 V
• Low-current power supply : IDD (VDD = 3 V) = 10 μA (typ.)
• Built-in phase-compensated op-amp, obviating the need for
any external device
• Ultra-compact package
TC75S55F
TC75S55FU
TC75S55FE
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Supply voltage
Differential input voltage
Input voltage
Power
dissipation
TC75S55F/FU
TC75S55FE
Operating temperature
Storage temperature
Symbol
VDD, VSS
DVIN
VIN
PD
Topr
Tstg
Rating
7
±7
VDD~VSS
200
100
−40~85
−55~125
Unit
V
V
V
mW
°C
°C
Weight
SSOP5-P-0.95 : 0.014 g (typ.)
SSOP5-P-0.65A : 0.006 g (typ.)
SON5-P-0.50 : 0.003 g (typ.)
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
1 2007-11-01
Marking (top view)
TC75S55F/FU/FE
Pin Connection (top view)
54
SF
VDD
5
OUT
4
123
123
IN (+) VSS IN (−)
Electrical Characteristics
DC Characteristics (VDD = 3.0 V, VSS = GND, Ta = 25°C)
Characteristics
Input offset voltage
Input offset current
Input bias current
Common mode input voltage
Voltage gain (open loop)
Maximum output voltage
Common mode input signal
Rejection Ratio
Supply voltage rejection ratio
Supply current
Source current
Sink current
Symbol
VIO
IIO
II
CMVIN
GV
VOH
VOL
CMRR
SVRR
IDD
Isource
Isink
Test
Circuit
Test Condition
1 RS = 10 kΩ
⎯⎯
⎯⎯
2⎯
⎯⎯
3 RL >= 1 MΩ
4 RL >= 1 MΩ
2 VIN = 0.0~2.1 V
1 VDD = 1.8~7.0 V
5⎯
6⎯
7⎯
Min Typ. Max Unit
⎯ 2 10 mV
⎯ 1 ⎯ pA
⎯ 1 ⎯ pA
0.0 ⎯ 2.1 V
60 70 ⎯ dB
2.9 ⎯
⎯
V
⎯ ⎯ 0.1
60 70 ⎯ dB
60 70
⎯ 10
10 20
100 450
⎯
20
⎯
⎯
dB
μA
μA
μA
DC Characteristics (VDD = 1.8 V, VSS = GND, Ta = 25°C)
Characteristics
Input offset voltage
Input offset current
Input bias current
Common mode input voltage
Voltage gain (open loop)
Maximum output voltage
Supply current
Source current
Sink current
Symbol
VIO
IIO
II
CMVIN
GV
VOH
VOL
IDD
Isource
Isink
Test
Circuit
Test Condition
1 RS = 100 kΩ
⎯⎯
⎯⎯
2⎯
⎯⎯
3 RL >= 1 MΩ
4 RL >= 1 MΩ
5⎯
6⎯
7⎯
Min Typ. Max Unit
⎯ 2 10 mV
⎯ 1 ⎯ pA
⎯ 1 ⎯ pA
0.0 ⎯ 0.9 V
60 70 ⎯ dB
1.7 ⎯
⎯
V
⎯ ⎯ 0.1
⎯ 8 16 μA
8 16 ⎯ μA
100 400
⎯
μA
2 2007-11-01
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