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Datasheet IS61QDPB42M36 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 7 | IS61QDPB42M36 | QUADP (Burst of 4) Synchronous SRAMs 72 Mb (2M x 36 & 4M x 18) 7 QUADP (Burst. of 4) Synchronous SRAMs
IQ
May 2009
Features
• 2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data valid window.
• Separate read and write ports with concurrent read and write operations.
• Synchronous pipeline read with late write |
 ISSI |
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| 6 | IS61QDPB42M36A | 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2
4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
NOVEMBER 2014
FEATURES
2Mx36 and 4Mx18 configuration available.
On-chip Delay Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports wi |
ISSI |
|
| 5 | IS61QDPB42M36A1 | 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2
4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
NOVEMBER 2014
FEATURES
2Mx36 and 4Mx18 configuration available.
On-chip Delay Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports wi |
ISSI |
|
| 4 | IS61QDPB42M36A2 | 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2
4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
NOVEMBER 2014
FEATURES
2Mx36 and 4Mx18 configuration available.
On-chip Delay Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports wi |
ISSI |
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