|
|
PDF NDS355N Data sheet ( Hoja de datos )
| Número de pieza | NDS355N | |
| Descripción | N-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NDS355N (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
|
No Preview Available !
March 1996
NDS355N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMICA
cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline
surface mount package.
1.6A, 30V. RDS(ON) = 0.125Ω @ VGS = 4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
_______________________________________________________________________________
D
GS
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient (Note 1a)
Thermal Resistance, Junction-to -Case (Note 1)
© 1997 Fairchild Semiconductor Corporation
NDS355N
30
20
± 1.6
± 10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
NDS355N Rev. D1
1 page  
Typical Electrical Characteristics (continued)
1.15
1.1
I D = 250µA
1.05
1
0.95
0.9
-50
-25
0 25 50 75 100 125 150 175
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation
with Temperature
20
1 0 VGS = 0V
1
TJ = 125°C
0.1
25°C
-55°C
0.01
0.001
0.2
0.4 0.6 0.8 1 1.2
VSD , BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature
500
300 C iss
200
C oss
100
50
30
f = 1 MHz
V GS = 0V
C rss
0.1 0.2
0.5 1
2
5 10
VDS , DRAIN TO SOURCE VOLTAGE (V)
30
Figure 9. Capacitance Characteristics
10
I = 1.6A
D
8
6
VDS = 5V
10
15
4
2
0
012345
Qg , GATE CHARGE (nC)
Figure 10. Gate Charge Characteristics
6
7
VIN
VGS
RGEN
G
VDD
RL
D
V OUT
DUT
S
t d(on)
t on
tr
90%
t d(off)
toff
tf
90%
Output, Vout
Input, Vin
10%
10%
50%
10%
90% Inverted
50%
Pulse Width
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
NDS355N Rev. D1
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NDS355N.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NDS355AN | N-Channel Logic Level Enhancement Mode Field Effect Transistor | Fairchild |
| NDS355N | N-Channel Logic Level Enhancement Mode Field Effect Transistor | Fairchild |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |