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PDF MAX2986 Data sheet ( Hoja de datos )
| Número de pieza | MAX2986 | |
| Descripción | Integrated Powerline Digital Transceiver | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-3484; Rev 0; 11/04
Integrated Powerline Digital Transceiver
General Description
The MAX2986 powerline transceiver utilizes state-of-the-
art CMOS design techniques to deliver the highest level
of performance and flexibility. This highly integrated
design combines the media access control layer (MAC)
and the physical layer (PHY) in a single chip. The
MAX2986 digital baseband and its companion device,
the MAX2980* analog front-end (AFE), offer a complete
high-speed powerline communication solution that is fully
compatible with third-party HomePlug® 1.0 devices.
The MAX2986 digital transceiver utilizes Maxim’s
advanced OFDM powerline engine with adaptive data
rates up to 14Mbps. The MAX2986’s open architecture
allows extensive programmability, feature enhancement
capability, and improved testability in the MAC for opti-
mum performance. Hence, this device is aimed at appli-
cations such as local area networks (LANs), audio,
voice, home automation, industrial automation, and
broadband-over-powerline (BPL), as well as spectral
shaping and tone notching capability, providing an
unparalleled level of flexibility to conform to the disparate
local regulatory bodies. Maxim’s modified OFDM tech-
nique allows shaping of power spectral density of the
transmitted signal arbitrarily to accommodate any
desired subcarrier set and to place spectral nulls at any
unwanted frequency location. The automatic channel
adaptation and interference rejection features of the
MAX2986 guarantee outstanding performance. Privacy
is provided by a 56-bit DES encryption with key manage-
ment.
The MAX2986 operates with IEEE 802.03 standard
media independent interface (MII), reduced media inde-
pendent interface (rMII), buffered FIFO data communica-
tion, IEEE 802.03 compatible 10/100 Ethernet MAC, or
USB 1.1 interfaces. These interfaces allow the MAX2986
to be paired with almost any data communication
devices to use in a variety of information appliances.
Applications
Broadband-Over-Powerline
Local Area Networks
(LANs)
Multimedia-Over-Powerline
Voice-Over-Powerline
Industrial Automation
(Remote Monitoring and
Control)
Home Automation
Security and Safety
Features
♦ Single-Chip Powerline Networking Transceiver
♦ Up to 14Mbps Data Rate
♦ 4.49MHz to 20.7MHz Frequency Band
♦ Upgradeable/Programmable MAC
Spectral Shaping Including Bandwidth and
Notching Capability
Programmable Preamble
Access to Application Protocol Interface (API)
128kB Internal SRAM
♦ JTAG Interface
♦ Large Bridge Table: Up to 512 Addresses
♦ 56-Bit DES Encryption with Key Management for
Secure Communication
♦ Advanced Narrowband Interference Rejection
Circuitry
♦ OFDM-Based PHY
84 Carriers
Automatic Channel Adaptation
FEC (Forward Error Correction)
DQPSK, DBPSK, ROBO
♦ On-Chip Interfaces
10/100 Ethernet
USB 1.1
MII/rMII/FIFO
♦ Compatible with HomePlug 1.0 Standard
PART
MAX2986CXV
Ordering Information
TEMP RANGE
0°C to +70°C
PIN-PACKAGE
144 CSBGA
*Future product—contact factory for availability.
HomePlug is a registered trademark of HomePlug Powerline
Alliance, Inc.
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Integrated Powerline Digital Transceiver
Pin Description (continued)
BUMP
NAME
FUNCTION
C10, D10,
E10, F10,
G10, J10, K10
VDD18
+1.8V Digital Power Supply. Bypass to DGND with a 100nF capacitor as close to the pin as possible.
C11 JTMS JTAG Test Mode Select
C12 JTDI JTAG Test Data Input
D2 USBRESET Active-Low USB Reset Signal. Connect to RESET.
D3 RESET Asynchronous, Active-Low Reset Input
E2 JRTCK JTAG Return Test Clock
E4 AFEFRZ Analog Front-End Carrier Sense Indicator
F1 AFETXEN Analog Front-End Transmitter Enable Output
F2 XIN Crystal Input (30MHz)
F3 XOUT Crystal Output
F11 MIITXEN MII Transmit Enable
G1 AFERESET AFE Reset
G2 AFEDAD[0] Analog Front-End DAC/ADC Input/Output 0 Interface
G3 AFEDAD[1] Analog Front-End DAC/ADC Input/Output 1 Interface
G4 AFEDAD[2] Analog Front-End DAC/ADC Input/Output 2 Interface
G11 JTDO JTAG Test Data Output
G12 JTRST Active-Low JTAG Test Reset
G13 JTCK JTAG Test Clock
H1 AFEDAD[3] Analog Front-End DAC/ADC Input/Output 3 Interface
H2 AFEDAD[4] Analog Front-End DAC/ADC Input/Output 4 Interface
H3 AFEDAD[5] Analog Front-End DAC/ADC Input/Output 5 Interface
H4 AFEDAD[6] Analog Front-End DAC/ADC Input/Output 6 Interface
H10 MIIRXDV MII Receive Data Valid
H11 BUFRD Active-Low FIFO Read Enable
H12 BUFCS Active-Low FIFO Chip Enable
H13 BUFWR Active-Low FIFO Write Enable
J2 AFEDAD[7] Analog Front-End DAC/ADC Input/Output 7 Interface
J3 AFEDAD[8] Analog Front-End DAC/ADC Input/Output 8 Interface
J4 AFEDAD[9] Analog Front-End DAC/ADC Input/Output 9 Interface
J11 MIIMDC MII Management Data Clock
J12 MIIDAT[7] MII/FIFO Transmit/Receive Data [7]
J13 MIIDAT[5] MII/FIFO Transmit/Receive Data [5]
K1 AFECLK 50MHz AFE Clock
K2 AFEREN Analog Front-End Read Enable Output
K3 AFEPDRX AFE Receiver Power-Down
K7 UARTTXD UART Transmit
K11 MIICRS MII Carrier Sense
K12 MIIDAT[6] MII/FIFO Transmit/Receive Data [6]
_______________________________________________________________________________________ 5
5 Page 
Integrated Powerline Digital Transceiver
MII Signal Timing—Receiving
When a frame is ready to send from the MAX2986 to
the external host, the MAX2986 asserts MIIRXDV after
IFG (which is about 0.96µs), while there is no transmis-
sion session in progress (with respect to MIICRS).
Note: The receive process cannot start while a trans-
mission is in progress.
While the MAX2986 keeps MIIRXDV high, data is sam-
pled synchronously with respect to MIICLK from the
MAX2986 through MIIDAT. After the last byte of data is
received, the MAX2986 resets MIIRXDV.
Receive timing of the MII interface is illustrated in
Figure 7, with details in Figure 8 and Table 4.
MIICLK
MIICRS
MIIRXDV
MIIDAT
IFG
DATA DATA
DATA DATA DATA
Figure 7. Receive Behavior of the MII Interface
MIIDAT
MIIRXDV
MIICRS
MIICLK
tOH
tOV
Figure 8. MII Interface—Detailed Receive Timing
Table 4. MII Interface—Detailed Receive
Timing*
PARAMETER
DESCRIPTION
tOV
Data valid after positive
edge of MIICLK
MAX UNITS
2.5 ns
One
tOH Nominal data hold time MIICLK ns
period
*Per IEEE 802.3u standard.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet MAX2986.PDF ] | |
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