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PDF ML2724 Data sheet ( Hoja de datos )
| Número de pieza | ML2724 | |
| Descripción | 2.4GHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet | |
| Fabricantes | Micro Linear | |
| Logotipo |  |
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ML2724
2.4GHz Low-IF 1.5Mbps FSK Transceiver
Final Datasheet
GENERAL DESCRIPTION
FEATURES
The ML2724 is a fully integrated 1.5Mbps frequency
shift keyed (FSK) transceiver that operates in the
unlicensed 2.4GHz ISM frequency band. The device
has been optimized for digital cordless telephone
applications and includes all the frequency generation,
receive and transmit functions. Automatically adjusted
filters eliminate mechanical tuning. Closed loop
modulation eliminates frequency drift and permits
practically unlimited TX duration. The transmitter
generates a 3dBm FSK output signal.
The 1.5Mbps data rate permits data spreading, such as
Direct Sequence Spread Spectrum (DSSS) modulation,
which improves range. The dual conversion Low-IF
receiver has all of the sensitivity and selectivity
advantages of a traditional super-heterodyne without
requiring costly, bulky external filters, while providing
the integration advantages of direct conversion.
The phase locked loop (PLL) synthesizer is completely
integrated, including the voltage controlled oscillator
(VCO), tuning circuits, and VCO resonator. This allows
the ML2724 to be used in frequency hopped spread
spectrum (FHSS) applications.
The ML2724 contains internal voltage regulation. It
also contains PLL and transmitter configuration
registers. The device can be placed in a low power
standby mode for current sensitive applications. It is
packaged in a 32TQFP.
PIN CONFIGURATION
XCEN
RXON
PAON
EN
DATA
CLK
AOUT
VSS
132 31 30 29 28 27 26 2524
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
VCCA
RVLO
TXOB
TXO
GNDRXMX2
GNDRXMX
GNDRF
RXI
ORDERING INFORMATION
PART # TEMP RANGE
PACKAGE
SPEC
ML2724DH -10oC to +60 oC 32 Pin TQFP 7mmx7mm DS2724-F-01
DS2724-F-01
Complete 2.4GHz FSK Transceiver
- High data rate (1.5Mbps)
- -90dBm sensitivity (DSSS modulation)
- 3dBm Output Power (differential, typical)
Closed Loop TX Modulation
Low IF Receiver: No external IF filters required.
Fully Integrated frequency synthesizer:
- No external resonator required.
Sigma-Delta Fractional-N two-port modulator
Automatic Filter Alignment
- No manufacturing adjustments required.
No external data slicer components required
Control outputs correctly sequence and control PA
3-wire control interface
Analog RSSI output
APPLICATIONS
2.4GHz FSK Data Transceivers
- Digital Cordless Telephones
- Wireless PC Peripherals
- Wireless Game Controllers
- Wireless Streaming Media
BLOCK DIAGRAM
RXI
2.4 GHz
Receive Input
TXO/TXOB
2.4 GHz
Output
Transmit
Mixer
2
Bandgap
Quadrature
Downmixers
Filter
Alignment
Divide
by 2
Quadrature
Divider
F
to
V
RSSI
Test Mux
Mode
Control
Two-port
Modulator
1.6 GHz
VCO
PLL
Divider
P.D.
Control
Registers
Ref.
Divider
AOUT
DOUT
Receive Data
Out
RSSI
TPC
PAON
RXON
XCEN
Parallel
control lines
DIN
Transmit Data In
DATA
CLK
Serial
Control Bus
EN
FREF
Frequency
Reference
VTUNE
QPO
PLL Loop
Filter
APRIL 2003
1 page  
ML2724
SYMBOL PARAMETER
fFREF
Reference signal frequency
VFREF Reference signal input level
RECEIVER
ZIN
NF
DRRX
S
Receiver input impedance
Receiver noise figure
Data Rate
Input Sensitivity
BWRX
PIMAX
Bandwidth
Maximum RX RF input
IIP3 Receiver Input IP3
LO leakage at RXI
IRR Mixer Image Rejection Ratio
Adjacent channel rejection
IF FILTERS
fIFC
BWIF
IF filter center frequency
IF filter 3dB bandwidth
LIMITER, AGC, AND FM DEMODULATOR
tOVLD
Recovery from overload
Eb/No
Co-Channel rejection, 10-3 BER
VODC
VOPK
VOL
Quiescent voltage @ AOUT
Output voltage swing AOUT
AOUT open-drain voltage
RSSI PERFORMANCE
tRRSSI
tFRSSI
GRSMID
VRSMX
VRSMD
RSSI rise time No Signal to
-15dBm into the IF mixer
RSSI fall time, < -15dBm to
No Signal into the IF mixer
RSSI sensitivity
RSSI maximum voltage
RSSI midrange voltage
CONDITIONS
MIN TYP MAX UNITS
6.144
12.288
MHz
MHz
6.144MHz or 12.288MHz sine wave,
capacitively coupled
2.0
VCCA
VPP
fc=2445MHz
fc=2445MHz
FSK modulation, fdev=+/-512KHz
<12.5% CER at 1.536Mchip/s
<10e-3 BER at 1.536Mbps
3dB Bandwidth
<12.5% CER at 1.536Mchip/s
<10e-3 BER at 1.536Mb/s
Test tones 2 and 4 channels away
Measured at 3.5MHz offset
-80dBm wanted signal <10-3 BER
Single 2GFSK modulated interferer
with a 1.5MHz –20dBc bandwidth
1 channel away
2 channels away
3 or more channels away
2.2+j0
16.5
1.536
-82 -90
-81
770
+5
-4
-15
-60
35
6
31
36
Ω
dB
Mbps
dBm
dBm
kHz
dBm
dBm
dBm
dBm
dB
dB
dB
dB
After Automatic Filter Alignment
After Automatic Filter Alignment
1.024
1405
MHz
kHz
From +15dBm at input
For 10-3 BER
-80 dBm, modulated with
1.536Mbps GFSK, BT=0.5, PRBS
data
IO=100µA, TPC Mode
5 12
10.5
10.5
1.1
0.55
1.1
0.4
µs
dB
dB
V
VPP
V
20 pF load, 20% to 80%
20 pF load, 20% to 80%
(V-40dBm – V-60dBm)/20dB
See Figure 3
-40 dBm into RXI
4.5 µs
3.0 µs
28 36 42 mV/dB
1.8 2.3
V
1.4 1.7 2.0
V
DS2724-F-01
FINAL DATASHEET
APRIL 2003
5
5 Page 
PIN SIGNAL
NAME
11 QPO
I/O FUNCTION
O Charge Pump Output of the phase
detector. This is connected to the
external PLL loop filter.
ML2724
DIAGRAM
RVPLL
10
11 QPO
15 VTUNE
26 VBG
28 RSSI
I VCO Tuning Voltage input from the PLL
loop filter. This pin is very sensitive to
noise coupling and leakage currents.
8
VSS
VCCA
24
1.25V
VTUNE 15
3.7k
O Bandgap Decouple Voltage. Decoupled N/A
to ground with a 220nF capacitor.
O Buffered Analog RSSI output with a
nominal sensitivity of 35mV/dB. In analog
test modes, this pin and the AOUT output
become test access points controlled by
the serial control bus.
8
VSS
TPI
MUX
VCCA
24
RSSI
OP
AMP
RSSI
MUX
100 Ω
28 RSSI
8
VSS
DS2724-F-01
FINAL DATASHEET
APRIL 2003
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet ML2724.PDF ] | |
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