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PDF RT9645 Data sheet ( Hoja de datos )
| Número de pieza | RT9645 | |
| Descripción | 5 Channels ACPI Regulator | |
| Fabricantes | Richtek Technology Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de RT9645 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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Preliminary
RT9645
5 Channels ACPI Regulator
General Description
The RT9645 is a combo regulator which is compliant to
ACPI specification for desktop/server power management
and system application. The part features one switching
regulator for DDR memory VDDQ power; a second PWM
controller for GMCH core power, a LDO controller for
www.DataShFeSeBt4_U.VcoTmT termination, a LDO controller for 5VSB to 3VSB
conversion; and a dual power control 5VDL for S0 and S3
system power.
The part is generally operated to conform to ACPI
specification. In S3 mode, only VDDQ and 3.3VSB
regulators remain on while the FSB_ VTT regulator is off.
In the transition from S3 to S0, an internal SS capacitor is
attached for linear regulators to control its slew rate
respectively to avoid inrush current induced.
RT9645 supports both Intel VR11 and AMD K8 platform.
There is extra control pin VTT_EN to enable FSB_VTT
regulator at AMD K8 mode. This part also implements
PWM1 (VDDQ) enabled by release COMP1 at AMD K8
application. This part is assemblyed in the tiny
VQFN-24L 4x4 package.
Ordering Information
RT9645
Package Type
QV : VQFN-24L 4x4
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
Note :
Richtek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
Features
z Integrated 5 Channels Power Regulator
z DC/DC Buck PWM Regulator (Driver Included)
z DC/DC Buck PWM Controller
z Linear Regulator Controller for FSB_VTT Power
z 3.3VSB Linear Regulator Controller with 40mA
Output Capability
z 5VDL Switch Control
z Conform to ACPI Specification, Supporting Power
Management at S0, S3, and S5 State
z 300kHz Fixed Frequency Oscillator
z Low-Side RDS(ON) Current Sensing for Precision
Over-Current Detection
z Thermal Shutdown
z Small 24-Lead VQFN Package
z RoHS Compliant and 100% Lead (Pb)-Free
Applications
z Desktop System Power
z Server System Power
Pin Configurations
(TOP VIEW)
24 23 22 21 20 19
SB3V_DRV 1
18 VTT_DRV
VDD 2
17 VTT_SEN
PWM2 3
SS2/EN2 4
PGND
16 VTT_EN
15 ISNS2
COMP2 5
FB2 6
14 FB1
25
13 COMP1
7 8 9 10 11 12
VQFN-24L 4x4
DS9645-00 August 2007
www.richtek.com
1
1 page  
Function Block Diagram
Preliminary
RT9645
SS2/EN2 FB2
FB COMP1
COMP2
www.DataSheet4UP.cWoMm2
SB3V_SEN
SB3V_DRV
EN_Detect
SS
-
+
+
-
VDD 70k
-
+
+
-
35k
+
-
VREF
-
UV +
VREF
PVIN
VTT_DRV
VTT_EN
VTT_SEN
VDD
+
--
+
VDDQ UV
or
FSB-VTT UV
VDDQ OC
SB3V Fault (UV &OC)
Thermal shut_down
Back S5
Hiccup
Digital &
Peripheral Control
EN_Detect
-
++
-
Oscillator
BOOT
UGATE
PHASE
PVIN
LGATE
IOC2
40uA
- ISNS2
+
IOC1
40uA
- ISNS
+
PVIN
VDD
VCC_DRV
SB5V_DRV
GND
S3 S5
DS9645-00 August 2007
www.richtek.com
5
5 Page 
Preliminary
RT9645
100 FZ1 FZ2 FP1 FP2
80
60 Open Loop Error
AMP Gain
40
20
20LOG
(R1/R2)
0
-20 Modulator
Gain
-40
w w w . D a t a S h e e t 4 U . c o m FLC
-60
10 100 1K
20LOG
(VIN/ΔVOSC)
Compensation
Gain
FESR
10K 100K
Closed Loop Gain
1M 10M
Frequency (Hz)
Figure 8
Feedback Loop Design Procedure
Use these guidelines for locating the poles and zeros of
the compensation network :
1. Pick Gain (R2/R1) for desired 0dB crossing frequency
(FC).
2. Place 1st zero FZ1 below modulator double pole FLC
(~75% FLC).
3. Place 2nd zero FZ2 at modulator double pole FLC.
4. Place 1st pole FP1 at the ESR zero FZ_ESR
5. Place 2nd pole FP2 at half the switching frequency.
6. Check gain against error amplifier's open-loop gain.
7. Pick RFB for desired output voltage.
8. Estimate phase margin and repeat if necessary.
Component Selection
Components should be appropriately selected to ensure
stable operation, fast transient response, high efficiency,
minimum BOM cost and maximum reliability.
Output Inductor Selection
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. For a synchronous buck converter, the ripple
current of inductor (%IL) can be calculated as follows :
ΔIL
= (VIN
− VOUT ) ×
VOUT
VIN × IOSC × L
(7)
Generally, an inductor that limits the ripple current between
20% and 50% of output current is appropriate. Make sure
that the output inductor could handle the maximum output
current and would not saturate over the operation
temperature range.
Output Capacitor Selection
The output capacitors determine the output ripple voltage
(%VOUT) and the initial voltage drop after a high slew rate
load transient. The selection of output capacitor depends
on the output ripple requirement. The output ripple voltage
is described as Equation (8).
ΔVOUT
=
ΔIL
× ESR +
1×
8 IO2 SC
VOUT
× L × COUT
(1− D)
(8)
For electrolytic capacitor application, typically 90 to 95%
of the output voltage ripple is contributed by the ESR of
output capacitors. Paralleling lower ESR ceramic capacitor
with the bulk capacitors could dramatically reduce the
equivalent ESR and consequently the ripple voltage.
Input Capacitor Selection
Use mixed types of input bypass capacitors to control
the input voltage ripple and switching voltage spike across
the MOSFETs. The buck converter draws pulsewise
current from the input capacitor during the on time of upper
MOSFET. The RMS value of ripple current flowing through
the input capacitor is described as :
IIN(RMS) = IOUT × D × (1− D)
The input bulk capacitor must be cable of handling this
ripple current. Sometime, for higher efficiency the low ESR
capacitor is necessarily. Appropriate high frequency
ceramic capacitors physically near the MOSFETs
effectively reduce the switching voltage spikes.
MOSFET Selection of PWM Buck Converter
The selection of MOSFETs is based upon the
considerations of RDS(ON), gate driving requirements, and
thermal management requirements. The power loss of
upper MOSFET consists of conduction loss and switching
loss and is expressed as :
PUPPER = PCOND _ UPPER + PSW _ UPPER
=
IO2 UT
× RDS(ON)
×D
+
1
2
IOUT
×
VIN
×
(TRISE
+
TFALL
) × IOSC
DS9645-00 August 2007
www.richtek.com
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet RT9645.PDF ] | |
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