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PDF MAX8794 Data sheet ( Hoja de datos )
| Número de pieza | MAX8794 | |
| Descripción | Low-Voltage DDR Linear Regulator | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-0584; Rev 0; 8/06
EVAALVUAAILTAIOBNLEKIT
Low-Voltage DDR Linear Regulator
General Description
The MAX8794 DDR linear regulator sources and sinks up
to 3A peak (typ) using internal n-channel MOSFETs. This
linear regulator delivers an accurate 0.5V to 1.5V output
from a low-voltage power input (VIN = 1.1V to 3.6V). The
MAX8794 uses a separate 3.3V bias supply to power the
control circuitry and drive the internal n-channel MOSFETs.
The MAX8794 provides current and thermal limits to pre-
vent damage to the linear regulator. Additionally, the
MAX8794 generates a power-good (PGOOD) signal to
indicate that the output is in regulation. During startup,
PGOOD remains low until the output is in regulation for 2ms
(typ). The internal soft-start limits the input surge current.
The MAX8794 powers the active-DDR termination bus
that requires a tracking input reference. The MAX8794
can also be used in low-power chipsets and graphics
processor cores that require dynamically adjustable
output voltages. The MAX8794 is available in a 10-pin,
3mm x 3mm, TDFN package.
Applications
Notebook/Desktop Computers
DDR Memory Termination
Active Termination Buses
Graphics Processor Core Supplies
Chipset/RAM Supplies as Low as 0.5V
Features
♦ Internal Power MOSFETs with Current Limit (3A typ)
♦ Fast Load-Transient Response
♦ External Reference Input with Reference
Output Buffer
♦ 1.1V to 3.6V Power Input
♦ ±15mV (max) Load-Regulation Error
♦ Thermal-Fault Protection
♦ Shutdown Input
♦ Power-Good Window Comparator with 2ms (typ)
Delay
♦ Small, Low-Profile, 10-Pin, 3mm x 3mm TDFN
Package
♦ Ceramic or Polymer Output Capacitors
Ordering Information
PART
TEMP PIN-
RANGE PACKAGE
TOP
MARK
MAX8794ETB+
-40°C to
+85°C
10 TDFN
(3mm x 3mm)
ABD
+Denotes lead-free package.
PKG
CODE
T1033-1
Pin Configuration
TOP VIEW
REFOUT 1
VCC 2
AGND 3
REFIN 4
PGOOD 5
MAX8794
10 IN
9 OUT
8 PGND
7 SHDN
6 OUTS
TDFN
3mm x 3mm
Typical Operating Circuit
VIN
(1.1V TO 3.6V)
IN
OUT
OUTS
VOUT = VTT
VBIAS
(2.7V TO 3.6V)
VDDQ
(2.5V OR 1.8V)
MAX8794
VCC PGND
SHDN
AGND
PGOOD
REFIN
REFOUT
VREFOUT = VTTR
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Low-Voltage DDR Linear Regulator
Typical Operating Characteristics (continued)
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
20
15
10
5
0
-5
-10
-15
-20
-10
REFOUT VOLTAGE ERROR
vs. REFOUT LOAD CURRENT
-5 0 5
REFOUT LOAD CURRENT (mA)
10
STARTUP WAVEFORM
5VMAX8794 toc11
SHDN
0V
500µs/div
1.25V
VOUT
0V
4V
PGOOD
0V
SHUTDOWN WAVEFORM
5VMAX8794 toc12
RLOAD = 100Ω SHDN
0V
2V
1V
VOUT
0V
4V
PGOOD
0V
100µs/div
SOURCE/SINK LOAD TRANSIENT
MAX8794 toc14
VOUT
AC-COUPLED
5mV/div
4.00µs/div
+1.5A
IOUT
-1.5A
SOURCE LOAD TRANSIENT
MAX8794 toc13
VOUT
AC-COUPLED
1mV/div
20.0µs/div
1A
IOUT
0A
LINE TRANSIENT
MAX8794 toc15
3.3V
VIN (1V/div)
1.5V
VOUT (10mV/div)
AC-COUPLED
0.9V
40µs/div
IOUT = 100mA
_______________________________________________________________________________________ 5
5 Page 
Low-Voltage DDR Linear Regulator
For a step-voltage change at REFIN, the rate of change
of the output voltage is limited by the total output
capacitance, the current limit, and the load during the
transition. Adding a capacitor across REFIN and AGND
filters noise and controls the rate of change of the
REFIN voltage during dynamic transitions. With the
additional capacitance, the REFIN voltage slews
between the two set points with a time constant given
by REQ x CREFIN, where REQ is the equivalent parallel
resistance seen by the slew capacitor.
Operating Region and Power Dissipation
The maximum power dissipation of the MAX8794
depends on the thermal resistance of the 10-pin TDFN
package and the circuit board, the temperature differ-
ence between the die and ambient air, and the rate of
airflow. The power dissipated in the device is:
PSRC = ISRC x (VIN – VOUT)
PSINK = ISINK x VOUT
The resulting maximum power dissipation is:
PDIS(MAX)
=
TJ(MAX) - TA
θJC + θCA
where TJ(MAX) is the maximum junction temperature
(+150°C), TA is the ambient temperature, θJC is the
thermal resistance from the die junction to the package
case, and θCA is the thermal resistance from the case
through the PC board, copper traces, and other materi-
als to the surrounding air. For optimum power dissipa-
tion, use a large ground plane with good thermal
contact to the backside pad, and use wide input and
output traces.
When 1in2 of copper is connected to the device, the
maximum allowable power dissipation of a 10-pin TDFN
package is 1951mW. The maximum power dissipation is
derated by 24.4mW/°C above TA = +70°C. Extra copper
on the PC board increases thermal mass and reduces
thermal resistance of the board. Refer to the MAX8794
evaluation kit for a layout example.
The MAX8794 delivers up to 3A and operates with input
voltages up to 3.6V, but not simultaneously. High output
currents can only be achieved when the input-output
differential voltages are low (Figure 5).
Dropout Operation
A regulator’s minimum input-to-output voltage differen-
tial (dropout voltage) determines the lowest usable sup-
ply voltage. Because the MAX8794 uses an n-channel
pass transistor, the dropout voltage is a function of the
drain-to-source on-resistance (RDS(ON) = 0.25Ω max)
multiplied by the load current (see the Typical
Operating Characteristics):
SAFE OPERATING REGION
3.5
DROPOUT VOLTAGE
3.0 LIMITED
MAXIMUM CURRENT LIMIT
2.5
2.0
TA = 0°C TO +70°C
1.5
VIN(MAX) - VOUT(MIN)
1.0
0.5
0
0
TA = +100°C
0.5 1.0 1.5 2.0 2.5 3.0 3.5
INPUT-OUTPUT DIFFERENTIAL VOLTAGE (V)
Figure 5. Power Operating Region—Maximum Output Current
vs. Input-Output Differential Voltage
VDROPOUT = RDS(ON) x IOUT
For low output-voltage applications, the sink current is
limited by the output voltage and the RDS(ON) of the
MOSFET.
Input Capacitor Selection
Bypass IN to PGND with a 10µF or greater ceramic
capacitor. Bypass VCC to AGND with a 1µF ceramic
capacitor for normal operation in most applications.
Typically, the LDO is powered from the output of a
step-down controller (memory supply) that has addi-
tional bulk capacitance (polymer or tantalum) and dis-
tributed ceramic capacitors.
Output Capacitor Selection
The MAX8794 output stability is independent of the out-
put capacitance for COUT from 10µF to 220µF.
Capacitor ESR between 2mΩ and 50mΩ is needed to
maintain stability. Within the recommended capaci-
tance and ESR limits, the output capacitor should be
chosen to provide good transient response:
∆IOUT(P-P) x ESR = ∆VOUT(P-P)
where ∆IOUT(P-P) is the maximum peak-to-peak load-
current step (typically equal to the maximum source
load plus the maximum sink load), and ∆VOUT(P-P) is
the allowable peak-to-peak voltage tolerance.
Using larger output capacitance can improve efficiency
in applications where the source and sink currents
change rapidly. The capacitor acts as a reservoir for
the rapid source and sink currents, so no extra current
is supplied by the MAX8794 or discharged to ground,
improving efficiency.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MAX8794.PDF ] | |
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