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PDF MC14076B Data sheet ( Hoja de datos )
| Número de pieza | MC14076B | |
| Descripción | 4-Bit D-Type Register with Three-State Outputs | |
| Fabricantes | ON Semiconductor | |
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MC14076B
4-Bit D-Type Register
with Three-State Outputs
The MC14076B 4–Bit Register consists of four D–type flip–flops
operating synchronously from a common clock. OR gated
output–disable inputs force the outputs into a high–impedance state
for use in bus organized systems. OR gated data–disable inputs cause
the Q outputs to be fed back to the D inputs of the flip–flops. Thus they
are inhibited from changing state while the clocking process remains
undisturbed. An asynchronous master root is provided to clear all four
flip–flops simultaneously independent of the clock or disable inputs.
• Three–State Outputs with Gated Control Lines
• Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing
• Asynchronous Master Reset
• Four Bus Buffer Registers
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
Unit
V
V
mA
PD Power Dissipation,
per Package (Note 2.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14076BCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
14076B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14076BCP
PDIP–16
2000/Box
MC14076BD
SOIC–16
2400/Box
MC14076BDR2 SOIC–16 2500/Tape & Reel
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14076B/D
1 page  
MC14076B
INPUT RISE AND FALL 20 ns
INPUT
D INFORMATION
tsu
90%
50%
10%
th
tsu
50%
tPLH
Q OUTPUT
tWH
fcl
90%
10%
tWL
tTLH
th
20 ns
90%
10%
VDD
VSS
VDD
VSS
tPHL
VOH
50%
VOL
tTHL
RESET = 0
DATA DISABLE A AND B = 0
OUTPUT DISABLE A AND B = 0
Figure 1. Timing Diagram
OUTPUT
DISABLE
A OR B
ANY Q
OUTPUT
ANY Q
OUTPUT
20 ns
90%
50% 50%
tPLZ
10%
tPHZ
90%
20 ns
10%
90%
tPZL
tPZH
10%
VDD
VSS
VOH
≈ 2.5 V @ VDD = 5 V,
10 V, AND 15 V
≈ 2 V @ VDD = 5 V
≈ 6 V @ VDD = 10 V
≈ 10 V @ VDD = 15 V
VOL
OUTPUTS
CONNECTED
OUTPUTS
DISCONNECTED
OUTPUTS
CONNECTED
OTHER
INPUTS
OUTPUT
DISABLE
A OR B
MC14076B
ANY Q
OUTPUT
RL = 1 kΩ
CL
VDD FOR tPLZ AND tPZL
VSS FOR tPHZ AND tPZH
Figure 2. Three–State Propagation Delay
Waveshape and Circuit
EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM
OUTPUT DISABLE A 1
OUTPUT DISABLE B 2
D0 14
DATA DISABLE A 9
DATA DISABLE B 10
DQ
C RQ
3 Q0
D1 13
CLOCK 7
DQ
C RQ
4 Q1
D2 12
DQ
C RQ
5 Q2
D3 11
RESET 15
DQ
C RQ
6 Q3
http://onsemi.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC14076B.PDF ] | |
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