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PDF MC10E142 Data sheet ( Hoja de datos )

Número de pieza MC10E142
Descripción 9-BIT SHIFT REGISTER
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MC10E142, MC100E142
5V ECL 9-Bit Shift Register
Description
The MC10E/100E142 is a 9-bit shift register, designed with
byte-parity applications in mind. The E142 performs serial/parallel in
and serial/parallel out, shifting in one direction. The nine inputs
D0 D8 accept parallel input data, while S-IN accepts serial input
data. The Qn outputs do not need to be terminated for the shift
operation to function. To minimize noise and power, any Q output not
used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes
of operation SHIFT and LOAD. The shift direction is from bit 0 to
bit 8. Input data is accepted by the registers a set-up time before the
positive going edge of CLK1 or CLK2; shifting is also accomplished
on the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero.
The 100 Series contains temperature compensation.
Features
700 MHz Min. Shift Frequency
9-Bit for Byte-Parity Applications
Asynchronous Master Reset
Dual Clocks
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
PbFree = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 405 devices
PbFree Packages are Available*
http://onsemi.com
PLCC28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE142G
AWLYYWW
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
February, 2006 Rev. 7
1
Publication Order Number:
MC10E142/D

1 page




MC10E142 pdf
MC10E142, MC100E142
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = 5.0 V (Note 9)
40°C
25°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min
fSHIFT
tPLH
tPHL
Maximum Toggle Frequency
Propagation Delay to Output
700
CLK 600
MR 600
900 700
800 1000 600
800 1000 600
900 700
800 1000 600
800 1000 600
tS Setup Time
D 50 100
SEL 300 150
50 100
300 150
50
300
tH Hold Time
D 300
SEL 75
100
150
300 100
75 150
300
75
tSKEW
Within-Device Skew (Note 10)
D to Q
75
75
tRR
tSKEW
tJITTER
tr, tf
Reset Recovery Time
Within-Device Skew (Note 10)
Random Clock Jitter (RMS)
Rise/Fall Times
(20 - 80%)
900 700
75
<1
900 700
75
<1
900
300 525 800 300 525 800 300
85°C
Typ
900
800
800
100
150
100
150
75
700
75
<1
525
Max
1000
1000
Unit
MHz
ps
ps
ps
ps
ps
ps
ps
ps
800
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary 0.46 V / +0.06 V.
100 Series: VEE can vary 0.46 V / +0.8 V.
10. Within-device skew is defined as identical transitions on similar paths through a device.
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
http://onsemi.com
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