PDF HYS72D32500GR-7F-B Data sheet ( Hoja de datos )

Número de pieza	HYS72D32500GR-7F-B
Descripción	Registered DDR SDRAM-Modules
Fabricantes	Infineon
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HYS 72Dxx5xxGR-7F/7/8-B Low Profile Registered DDR-I SDRAM-Modules 2.5 V Low Profile 184-pin Registered DDR-I SDRAM Modules 256MB, 512MB & 1GByte PC1600 & PC2100 Preliminary Datasheet Revision 0.91 • 184-pin Registered 8-Byte Dual-In-Line DDR-I SDRAM Module for “1U” PC, Workstation and Server main memory applications • One bank 32M × 72, 64M x 72 and two bank 128M × 72 organization • JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) with a single + 2.5 V (± 0.2 V) power supply • Built with DDR-I SDRAMs in 66-Lead TSOPII package • All inputs and outputs SSTL_2 compatible • Re-drive for all input signals using register and PLL devices. • Serial Presence Detect with E2PROM • Low Profile Modules form factor: 133.35 mm x 30,40 mm (1.2”) x 4.00 mm (6,80 mm with stacked components) • Based on Jedec standard reference card layouts RawCard “L”, “M”, “N” • Gold plated contacts • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Performance: -7F -7 -8 Unit Component Speed Grade DDR266F DDR266A DDR200 Module Speed Grade PC2100 PC2100 PC1600 fCK Clock Frequency (max.) @ CL = 2.5 143 143 125 MHz fCK Clock Frequency (max.) @ CL = 2 133 133 100 MHz The HYS72Dxx5x0GR are low profile versions of the standard Registered DIMM modules with 1.2” inch (30,40 mm) height for 1U Server Applications. The Low Profile DIMM versions are available as 32M x 72 (256MB), 64M x 72 (512MB) and 128M x 72 (1 GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. INFINEON Technologies 1 2002-08-16 (0.91) 1 page HYS 72Dxx5xxGR-7F/7/8-B Registered DDR-I SDRAM-Modules RS0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQS8 DQ31 DM8/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D0 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D3 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D8 DQS4 DM4/DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D4 DQS5 DM5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6/DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7/DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Serial PD DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D6 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D7 VDDSPD SCL A0 A1 A2 SA0 SA1 SA2 SDA VDD, VDDQ VREF V SS V DDID EEPROM D0 - D8 D0 - D8 D0 - D8 D0 - D8 Strap: see Note 4 CS0 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK R RS0 -> CS : SDRAMs D0-D8 E RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8 G RA0-RA12 -> A0-A12: SDRAMs D0 - D8 I RRAS -> RAS : SDRAMs D0 - D8 S T RCAS -> CAS : SDRAMs D0 - D8 E RCKE0 -> CKE: SDRAMs D0 - D8 R RWE -> WE : SDRAMs D0 - D8 RESET CK0, CK 0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, Adress and control resistors: 22 Ohms. 4. VDDID strap connections STRAP OUT (OPEN): VDD = VDDQ 5. SDRAM placement alternates between the back and front of the DIMM. Block Diagram: One Bank 32M x 72 DDR-I SDRAM DIMM Module (x8 components) HYS72D32500GR on Raw Card L INFINEON Technologies 5 2002-08-16 (0.91) 5 Page HYS 72Dxx5xxGR-7F/7/8-B Registered DDR-I SDRAM-Modules Operating, Standby and Refresh Currents (-7F: PC2100) Symbol Parameter/Condition 256MB 512MB 1GB x72 x72 x72 1bank 1bank 2bank Unit Notes -7F -7F -7F MAX MAX MAX 5 Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK IDD0 MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and 990 1980 2970 mA 1, 4 control inputs changing once every two clock cycles IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. 1080 2160 3150 mA 1, 3, 4 Precharge Power-Down Standby Current: all banks idle; power-down mode; IDD2P CKE <= VIL MAX; tCK = tCK MIN 72 144 288 mA 2, 4 Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE >= IDD2F VIH MIN; tCK = tCK MIN ,address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. 360 Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle; IDD2Q CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM. 225 720 1440 mA 2, 4 450 900 mA 2, 4 Active Power-Down Standby Current: one bank active; power-down mode; IDD3P CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM. 162 324 648 mA 2, 4 IDD3N Active Standby Current: one bank active; active / precharge;CS >= VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 495 990 1980 mA 2, 4 Operating Current: one bank active; Burst = 2; reads; continuous burst; IDD4R address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA 1035 2070 3060 mA 1, 3, 4 Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs IDD4W changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for 1125 2250 3240 mA 1, 4 DDR333; tCK = tCK MIN IDD5 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh 1620 3240 4230 mA 1, 4 IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN 23 45 90 mA 2, 4 IDD7 Operating Current: four bank; four bank interleaving with BL=4; Refer to the following page for detailed test conditions. 2025 4050 5040 mA 1, 3, 4 1. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for two bank modules (n: number of components per module bank) 3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents 5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C INFINEON Technologies 11 2002-08-16 (0.91) 11 Page

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