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PDF MC100E143 Data sheet ( Hoja de datos )
| Número de pieza | MC100E143 | |
| Descripción | 9-BIT HOLD REGISTER | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC100E143 (archivo pdf) en la parte inferior de esta página. Total 4 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
9ĆBit Hold Register
The MC10E/100E143 is a 9-bit holding register, designed with
byte-parity applications in mind. The E143 holds current data or loads
new data, with the nine inputs D0 – D8 accepting parallel input data.
• 700MHz Min. Operating Frequency
• 9-Bit for Byte-Parity Applications
• Asynchronous Master Reset
• Dual Clocks
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
The SEL (Select) input pin is used to switch between the two modes of
operation — HOLD and LOAD. Input data is accepted by the registers a
set-up time before the positive going edge of CLK1 or CLK2. A HIGH on
the Master Reset pin (MR) asynchronously resets all the registers to zero.
Pinout: 28-Lead PLCC (Top View)
SEL D8 D7 D6 D5 VCCO Q8
25 24 23 22 21 20 19
MR 26
18 Q7
CLK1 27
17 Q6
CLK2 28
16 VCC
VEE 1
15 Q5
NC 2
14 VCCO
D0 3
13 Q4
D1 4
12 Q3
5 6 7 8 9 10 11
D2 D3 D4 VCCO Q0 Q1 Q2
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0 – D8
SEL
CLK1, CLK2
MR
Q0 – Q8
NC
FUNCTIONS
SEL
L
H
Parallel Data Inputs
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
No Connection
Load
Hold
Function
Mode
12/93
© Motorola, Inc. 1996
2–1
MC10E143
MC100E143
9-BIT HOLD
REGISTER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0
MUX D
R
Q0
D1
MUX D
R
D
D2 MUX R
MUX D
D3 R
Q1
Q2
Q3
D8
SEL
CLK1
CLK2
MR
MUX D
R
Q8
REV 2
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet MC100E143.PDF ] | |
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