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PDF MC33592 Data sheet ( Hoja de datos )
| Número de pieza | MC33592 | |
| Descripción | PLL Tuned UHF Receiver | |
| Fabricantes | Freescale Semiconductor | |
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Technical Data
Freescale Semiconductor, Inc.
Romeo2
MC33592/D
Rev. 0, 7/2002
PLL Tuned UHF
Receiver for Data
Transfer Applications
FEATURES
• 315MHz, 434MHz Bands
• OOK Demodulation
• Low Current Consumption: 5mA Typ. in Run Mode
• Internal or External Strobing
• Fast Wake-Up Time (1ms)
• -105dBm RF Sensitivity (at 4.8kBd Data Rate)
• Fully Integrated VCO
• Image Cancelling Mixer
• Integrated IF Bandpass Filter at 660kHz
• IF Bandwidth: 300kHz
• ID Byte and Tone Detection
• Data Rate: 1 to 11kBd
• Manchester Coded Data Clock Recovery
• Fully Configurable by SPI Interface
• Few External Components, no RF Adjustment
Pin Connections
24 23 22 21 20 19
VCC 1
18 VCCDIG
VCC 2
17 SCLK
VCCLNA 3
16 MOSI
RFIN 4
15 MISO
GNDLNA 5
14 RESETB
GNDSUB 6
13 DMDAT
7 8 9 10 11 12
Figure 1: Simplified block diagram
Device
MC33592FTA
Table 1: Ordering Information
RF frequency/
IF filter bandwidth
Ambiant
Temperature Range
434MHz / 300kHz
-40°C to +85°C
Package
LQFP24
This document contains information on a new product under development. Motorola
reserves the right to change or discontinue this product without notice.
For More Information On This Product,
Go to: www.freescale.com
© Motorola, Inc., 2002
Free Datasheet http://www.datasheet4u.com/
1 page  
Freescale Semiconductor, Inc.
COMMUNICATION PROTOCOL
COMMUNICATION PROTOCOL
MANCHESTER CODING DESCRIPTION
Manchester coding is defined as follows: data is sent during the first half-bit, complementary data is sent
during the second half-bit.
Figure 3 : Manchester coding example
0 100110
Original data
Manchester coded
The signal average value is constant. This allows clock recovery from the data stream itself. In order to
achieve a correct clock recovery, Manchester coded data must have a duty cycle between 48% and 52%.
PREAMBLE, ID, HEADER WORDS AND MESSAGE DESCRIPTION
The following description applies if the Data Manager is enabled (DME=1).
The ID word is a Manchester coded byte whose content has been previously loaded in the Configuration
Register 2. The complement of the ID word is recognized as an ID word. ID word is sent at the same data rate as
data.
A preamble is required:
- before ID,
- before Header if HE=1,
- before data if HE=0.
It enables AGC to settle, and clock recovery. Figure 4 defines the Preamble word. Preamble content must be
carefully defined in order not to be decoded as an ID or Header word.
Figure 4 : Preamble definition
AGC settling time Clock recovery
ID
‘1’ NRZ > 200µs
i.e.:
2 ‘1’ NRZ at 9.6kBd,
1 ‘1’ NRZ at 4.8kBd
‘0’ Manchester
at data rate
The Header word is a 4 bit Manchester coded message ‘0110’ or its complement sent at the selected data
rate. This bit sequence and its complement must not be found in the sequence preamble and ID word.
Data must follow the Header without any delay.
Data are completed by a End-of-Message (EOM) word, consisting of 2 NRZ consecutive ones or zeroes. If the
complement of the Header word is received, output data are complemented too.
The following example shows a complete message with Preamble, ID, Header words followed by 2 data bits,
and an EOM. The preamble is placed at the beginning of both ID and Header words.
MOTOROLA
MC33592 Technical Data
For More Information On This Product,
Go to: www.freescale.com
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
Freescale Semiconductor, Inc.
CONFIGURATION REGISTERS
- DME enables the Data Manager:
0 = Disabled,
1 = Enabled.
Data are output on MOSI and the associated clock on SCLK.
- HE defines if a Header word is present (the bit HE is only active if DME=1):
0 = No header,
1 = Header.
Configuration Register 2 (CR2) defines the Identifier (ID) word content. The bits will be Manchester coded.
Bit name
Reset value
Table 7: Configuration Register 2
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
00000000
Table 8 describes the Configuration Register 3 (CR3).
Bit name
Reset value
Table 8: Configuration Register 3
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DR1 DR0 MG MS PG
-
-
-
10000000
- DR0/DR1 define the Data Rate (before Manchester coding) as shown onTable 9.
Table 9: Data Rate selection
DR1 DR0
Selected Ratio
00
1.0 - 1.4 kBd
01
2 - 2.7 kBd
10
4 - 5.3 kBd
11
8.6 - 10.6 kBd
- MG sets the mixer gain:
0 = Normal,
1 = -17dB (typical).
- MS switches the MIXOUT pin:
0 = To the mixer output,
1 = To the IF input.
Table 10: Mixer and MIXOUTconfiguration
MG MS
Mixer Gain
MIXOUT
00
Normal
Mixer output
01
Normal
IF input
10
Reduced
Mixer output
11
Forbidden, mixer test mode only
The combination MG=1, MS=1 is forbidden in any application. It configures the receiver in a test mode where
the mixer runs at fVCO/4.
- PG sets the phase comparator gain (see “The local oscillator PLL” chapter, page 4):
0 = High gain mode,
1 = Low gain mode.
MOTOROLA
MC33592 Technical Data
For More Information On This Product,
Go to: www.freescale.com
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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