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PDF CY7C1241V18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1241V18 | |
| Descripción | 36-Mbit QDR-II SRAM 4-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1241V18
CY7C1256V18
CY7C1243V18
CY7C1245V18
36-Mbit QDR™-II+ SRAM 4-Word
Burst Architecture (2.0 Cycle Read Latency)
Features
Functional Description
• Separate independent read and write data ports
— Supports concurrent transactions
• 300 MHz to 375 MHz clock for high bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write
ports (data transferred at 750 MHz) at 375 MHz
• Read latency of 2.0 clock cycles
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Single multiplexed address input bus latches address inputs
for both read and write ports
• Separate Port Selects for depth expansion
• Data valid pin (QVLD) to indicate valid data on the output
• Synchronous internally self-timed writes
• Available in x8, x9, x18, and x36 configurations
• Full data coherency providing most current data
• Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1]
• HSTL inputs and Variable drive HSTL output buffers
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1241V18 – 4M x 8
CY7C1256V18 – 4M x 9
CY7C1243V18 – 2M x 18
CY7C1245V18 – 1M x 36
The CY7C1241V18, CY7C1256V18, CY7C1243V18, and
CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with Quad Data Rate-II+ (QDR-II+) architecture.
QDR-II+ architecture consists of two separate ports to access
the memory array. The read port has dedicated data outputs
to support read operations and the write port has dedicated
data inputs to support write operations. QDR-II+ architecture
has separate data inputs and data outputs to completely
eliminate the need to “turn around” the data bus required with
common IO devices. Each port can be accessed through a
common address bus. Read and write addresses are latched
on alternate rising edges of the input (K) clock. Accesses to
the QDR-II+ read and write ports are completely independent
of one another. To maximize data throughput, both read and
write ports are equipped with Double Data Rate (DDR) inter-
faces. Each address location is associated with four 8-bit
words (CY7C1241V18), 9-bit words (CY7C1256V18), 18-bit
words (CY7C1243V18), or 36-bit words (CY7C1245V18), that
burst sequentially into or out of the device. Because data can
be transferred into and out of the device on every rising edge
of both input clocks (K and K), memory bandwidth is
maximized while simplifying system design by eliminating bus
“turn-arounds”.
Depth expansion is accomplished with Port Selects for each
port. Port selects enable each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
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375 MHz
375
1240
333 MHz
333
1120
300 MHz
300
1040
Unit
MHz
mA
Note
1.
The QDR consortium
VDDQ = 1.4V to VDD.
specification
for
VDDQ
is
1.5V
+
0.1V.
The
Cypress
QDR
devices
exceed
the
QDR
consortium
specification
and
are
capable
of
supporting
Cypress Semiconductor Corporation
Document Number: 001-06365 Rev. *C
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised May 11, 2007
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1 page  
CY7C1241V18
CY7C1256V18
CY7C1243V18
CY7C1245V18
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1243V18 (2M x 18)
1 2 3 4 56 7 8
A CQ NC/144M A
WPS BWS1
K NC/288M RPS
B NC Q9 D9 A
NC K BWS0 A
C NC
NC D10 VSS
A
NC
A VSS
D
NC
D11 Q10 VSS
VSS
VSS
VSS
VSS
E NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
N NC D17 Q16 VSS
A
A
A VSS
P NC NC Q17 A
A QVLD A
A
R
TDO
TCK
A
A
A NC A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
CY7C1245V18 (1M x 36)
1
A CQ
B Q27
C D27
D D28
E Q29
F Q30
G D30
H DOFF
J D31
K Q32
L Q33
M D33
www.DataSNheet4U.Dco3m4
P Q35
R TDO
23
NC/288M NC/72M
Q18 D18
Q28 D19
D20 Q19
D29 Q20
Q21 D21
D22 Q22
VREF
Q31
VDDQ
D23
D32 Q23
Q24 D24
Q34 D25
D26 Q25
D35 Q26
TCK
A
4
WPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
5
BWS2
BWS3
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
6
K
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
QVLD
NC
7
BWS1
BWS0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
A
10
NC/144M
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Document Number: 001-06365 Rev. *C
Page 5 of 28
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5 Page 
CY7C1241V18
CY7C1256V18
CY7C1243V18
CY7C1245V18
Write Cycle Descriptions
The write cycle description table for CY7C1241V18 and CY7C1243V18 follows.[2, 10]
BWS0/ BWS1/
NWS0 NWS1
K
K
Comments
L L L–H – During the data portion of a write sequence :
CY7C1241V18 − both nibbles (D[7:0]) are written into the device,
CY7C1243V18 − both bytes (D[17:0]) are written into the device.
L L – L-H During the data portion of a write sequence :
CY7C1241V18 − both nibbles (D[7:0]) are written into the device,
CY7C1243V18 − both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence :
CY7C1241V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1243V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence :
CY7C1241V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1243V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence :
CY7C1241V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1243V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence :
CY7C1241V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1243V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1256V18 follows.[2, 10]
BWS0
L
L
H
H
K
L–H
–
L–H
–
K Comments
– During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
– No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
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Note
10.
Assumes a write
a write cycle, as
cycle was initiated per the Write Cycle Description
long as the setup and hold requirements are met.
Table.
NWS0,
NWS1,
BWS0,
BWS1,
BWS2,
and
BWS3
can
be
altered
in
different
portions
of
Document Number: 001-06365 Rev. *C
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet CY7C1241V18.PDF ] | |
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