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PDF LP62S1024AM-70LLT Data sheet ( Hoja de datos )
| Número de pieza | LP62S1024AM-70LLT | |
| Descripción | 128K X 8 BIT LOW VOLTAGE CMOS SRAM | |
| Fabricantes | AMIC Technology | |
| Logotipo |  |
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LP62S1024A-T Series
128K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.7V to 3.6V
n Access times: 55/70 ns (max.)
n Current:
Very low power version: Operating:(70NS)30mA(max.)
(55NS)40mA(max.)
Standby:5uA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
n Data retention voltage: 2V (min.)
n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm)
forward type and 36-pin CSP packages
General Description
The LP62S1024A-T is a low operating current 1,048,576-
bit static random access memory organized as 131,072
words by 8 bits and operates on a low power voltage:
2.7V to 3.6V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n SOP
n TSOP/TSSOP
n CSP (Chip Size Package)
36-pin Top View
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O8
20 I/O7
19 I/O6
18 I/O5
17 I/O4
16 1
17 32
1234
A A0 A1 CE2 A3
B I/O5 A2 WE A4
56
A6 A8
A7 I/O1
C I/O6
NC A5
I/O2
D GND
VCC
E VCC
GND
F I/O7
NC NC
I/O3
G I/O8 OE CE1 A16 A15 I/O4
H A9 A10 A11 A12 A13 A14
Pin No.
Pin
Name
Pin No.
Pin
Name
12
A11 A9
17 18
A3 A2
3 4 5 6 7 8 9 10 11 12 13 14 15 16
A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
19 20 21 22 23 24 25 26 27 28 29 30 31 32
A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE
(August, 2001, Version 1.0)
1 AMIC Technology, Inc.
1 page  
LP62S1024A-T Series
DC Electrical Characteristics (continued)
Symbol
Parameter
LP62S1024A-55LLT/70LLT
Min.
Max.
ISB - 0.5
ISB1 Standby Power
Supply Current
ISB2
Output Low
VOL Voltage
Output High
VOH Voltage
-
-
-
2.2
5
5
0.4
-
Unit
mA
µA
µA
V
V
Conditions
CE1 = VIH or CE2 =VIL
CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
VIN ≥ 0V
CE2 ≤ 0.2V
VIN ≥ 0V
IOL = 2.1mA
IOH = -1.0mA
Truth Table
Mode
CE1 CE2
Standby
Output Disable
Read
Write
H
X
L
L
L
X
L
H
H
H
Note: X = H or L
OE
X
X
H
L
X
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Min.
CIN* Input Capacitance
CI/O*
Input/Output Capacitance
* These parameters are sampled and not 100% tested.
WE
I/O Operation
Supply Current
X
High Z
ISB, ISB1
X
High Z
ISB, ISB2
H
High Z
ICC, ICC1, ICC2
H DOUT
ICC, ICC1, ICC2
L DIN
ICC, ICC1, ICC2
Max.
6
8
Unit
pF
pF
Conditions
VIN = 0V
VI/O = 0V
(August, 2001, Version 1.0)
5 AMIC Technology, Inc.
5 Page 
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
LP62S1024A-T Series
0.4V to 2.4V
5 ns
1.5V
See Figures 1 and 2
TTL TTL
CL
30pF
CL
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Data Retention Characteristics (TA = -25°C to 85°C)
Symbol
VDR1
VDR2
Parameter
VCC for Data Retention
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Min.
2.0
2.0
Max.
3.6
3.6
Unit Conditions
V CE1 ≥ VCC - 0.2V
V CE2 ≤ 0.2V,
ICCDR1
Data Retention Current
- 3*
ICCDR2
- 3*
tCDR Chip Disable to Data Retention Time
tR Operation Recovery Time
0-
5-
* LP62S1024A-55LLT/70LLT ICCDR: max. 3µA at TA = 0°C to + 40°C
VCC = 2V,
µA CE1 ≥ VCC - 0.2V,
VIN ≥ 0V
VCC = 2V,
CE2 ≤ 0.2V,
µA VIN ≥ 0V
ns See Retention Waveform
ms
(August, 2001, Version 1.0)
11 AMIC Technology, Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet LP62S1024AM-70LLT.PDF ] | |
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