PDF STK12C68 Data sheet ( Hoja de datos )

Número de pieza	STK12C68
Descripción	8Kx8 AutoStore nvSRAM
Fabricantes	Simtek
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No Preview Available ! www.DataSheet4U.com STK12C68 (SMD5962-94599) 8Kx8 AutoStore nvSRAM FEATURES • 25, 35, 45, 55 ns Read Access & Write Cycle Time • Unlimited Read/Write Endurance • Automatic Non-volatile STORE on Power Loss • Non-Volatile STORE Under Hardware or Software Control • Automatic RECALL to SRAM on Power Up • Unlimited RECALL Cycles • 1 Million STORE Cycles • 100-Year Non-volatile Data Retention • Single 5V ± 10% Power Supply • Commercial, Industrial, Military Temperatures • 28-pin 330-mil SOIC, 300-mil PDIP, and 600-mil PDIP Packages (RoHS-Compliant) • 28-Pin CDIP and LCC Military Packages DESCRIPTION The Simtek STK12C68 is a 64Kb fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile stor- age cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The Simtek nvSRAM is the first monolithic non-vola- tile memory to offer unlimited writes and reads. It is the highest performance, most reliable non-volatile memory available. Block Diagram VCCX VCAP A5 A6 A7 A8 A9 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 QUANTUM TRAP 128 x 512 STATIC RAM ARRAY 128 X 512 STORE RECALL COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status. 1 POWER CONTROL STORE/ RECALL CONTROL SOFTWARE DETECT A0 – A12 G E W Document Control #ML0008 Rev 0.7 February 2007 1 page SRAM WRITE CYCLES #1 & #2 STK12C68 (SMD5962-94599) (VCC = 5.0V ± 10%)e SYMBOLS NO. #1 #2 Alt. PARAMETER STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55 UNITS MIN MAX MIN MAX MIN MAX MIN MAX 12 tAVAV 13 tWLWH 14 tELWH 15 tDVWH 16 tWHDX 17 tAVWH 18 tAVWL 19 tWHAX 20 tWLQZ i, j 21 tWHQX tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX tWC Write Cycle Time 25 35 45 55 ns tWP Write Pulse Width 20 25 30 45 ns tCW Chip Enable to End of Write 20 25 30 45 ns tDW Data Set-up to End of Write 10 12 15 25 ns tDH Data Hold after End of Write 0 0 0 0 ns tAW Address Set-up to End of Write 20 25 30 45 ns tAS Address Set-up to Start of Write 0 0 0 0 ns tWR Address Hold after End of Write 0 0 0 0 ns tWZ Write Enable to Output Disable 10 13 14 15 ns tOW Output Active after End of Write 5 5 5 5 ns Note j: If W is low when E goes low, the outputs remain in the high-impedance state. Note k: E or W must be ≥ VIH during address transitions. Note l: HSB must be high during SRAM WRITE cycles. SRAM WRITE CYCLE #1: W Controlledk, l ADDRESS E 12 tAVAV 14 tELWH 19 tWHAX 18 tAVWL W 17 tAVWH 13 tWLWH DATA IN 20 tWLQZ DATA OUT PREVIOUS DATA SRAM WRITE CYCLE #2: E Controlledk, l ADDRESS E 18 tAVEL 12 tAVAV 14 tELEH 15 tDVWH DATA VALID HIGH IMPEDANCE 16 tWHDX 21 tWHQX 19 tEHAX 17 tAVEH W DATA IN DATA OUT Document Control #ML0008 Rev 0.7 February 2007 13 tWLEH 15 tDVEH DATA VALID HIGH IMPEDANCE 5 16 tEHDX 5 Page HSB OPERATION The STK12C68 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven low, the STK12C68 will conditionally initiate a STORE operation after tDELAY; an actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK12C68 will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. The HSB pin can be used to synchronize multiple STK12C68s while using a single larger capacitor. To operate in this mode the HSB pin should be con- nected together to the HSB pins from the other STK12C68s. An external pull-up resistor to + 5V is required since HSB acts as an open drain pull down. The VCAP pins from the other STK12C68 parts can be tied together and share a single capacitor. The capacitor size must be scaled by the number of devices connected to it. When any one of the STK12C68s detects a power loss and asserts HSB, the common HSB pin will cause all parts to request a STORE cycle (a STORE will take place in those STK12C68s that have been written since the last nonvolatile cycle). During any STORE operation, regardless of how it was initiated, the STK12C68 will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK12C68 will remain disabled until the HSB pin returns high. STK12C68 (SMD5962-94599) If HSB is not used, it should be left unconnected. PREVENTING STORES The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30mA at a VOH of at least 2.2V, as it will have to overpower the internal pull-down device that drives HSB low for 20μs at the onset of a STORE. When the STK12C68 is connected for AutoStore operation (system VCC connected to VCCX and a 68μF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK12C68 will attempt to pull HSB low; if HSB doesn’t actually get below VIL, the part will stop try- ing to pull HSB low and abort the STORE attempt. HARDWARE PROTECT The STK12C68 offers hardware protection against inadvertent STORE operation and SRAM WRITEs dur- ing low-voltage conditions. When VCAP < VSWITCH, all externally initiated STORE operations and SRAM WRITEs are inhibited. AutoStore can be completely disabled by tying VCCX to ground and AutoStore Inhibit applying + 5V to VCAP . This is the mode; in this mode, STOREs are only initiated by explicit request using either the software sequence or the HSB pin. LOW AVERAGE ACTIVE POWER The STK12C68 draws significantly less current when it is cycled at times longer than 50ns. Figure 5 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial tem- perature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 6 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK12C68 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading. Document Control #ML0008 Rev 0.7 February 2007 11 11 Page

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