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PDF BS62LV8006 Data sheet ( Hoja de datos )
| Número de pieza | BS62LV8006 | |
| Descripción | Very Low Power/Voltage CMOS SRAM 1M X 8 bit | |
| Fabricantes | Brilliance | |
| Logotipo |  |
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BSI Very Low Power/Voltage CMOS SRAM
1M X 8 bit
BS62LV8006
FEATURES
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 75mA (@55ns) operating current
I -grade: 76mA (@55ns) operating current
C-grade: 60mA (@70ns) operating current
I -grade: 61mA (@70ns) operating current
8.0uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
GENERAL DESCRIPTION
The BS62LV8006 is a high performance , very low power CMOS Static
Random Access Memory organized as 1,048,576 words by 8 bits and
operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
8.0uA at 5V/25oC and maximum access time of 55ns at 5.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable (CE1)
, an active HIGH chip enable (CE2) and active LOW output enable (OE)
and three-state output drivers.
The BS62LV8006 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV8006 is available in 48B BGA and 44L TSOP2 packages.
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV8006EC
BS62LV8006FC
BS62LV8006EI
BS62LV8006FI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
55ns : 4.5~5.5V
70ns : 4.5~5.5V
+0 O C to +70OC 4.5V ~ 5.5V 55 / 70
-40 O C to +85OC 4.5V ~ 5.5V 55 / 70
POWER DISSIPATION
STANDBY
( ICCSB1, Max )
Operating
( ICC , Max )
Vcc=5V
Vcc=5V
55ns
55uA
75mA
110uA
76mA
PKG TYPE
TSOP2-44
BGA-48-0912
TSOP2-44
BGA-48-0912
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
GND
DQ2
DQ3
NC
NC
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BS62LV8006EC
BS62LV8006EI
44 A5
43 A6
42 A7
41 OE
40 CE2
39 A8
38 NC
37 NC
36 DQ7
35 DQ6
34 GND
33 VCC
32 DQ5
31 DQ4
30 NC
29 NC
28 A9
27 A10
26 A11
25 A12
24 A13
23 A14
123456
A
NC OE
A0
A1
A2 CE2
B NC NC A3 A4 CE1 NC
C
D0
NC A5
A6
NC D4
D VSS D1 A17 A7 D5 VCC
E VCC D2 VCC A16 D6 VSS
F
D3
NC A14
A15
NC
D7
G
NC
NC A12
A13
WE
NC
H A18 A8 A9 A10 A11 A19
FUNCTIONAL BLOCK DIAGRAM
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
Vdd
Gnd
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 X 4096
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
4096
8 Column I/O
Write Driver
Sense Amp
8
512
Column Decoder
18
Address Input Buffer
A11A9 A8 A3 A2 A1 A0A10 A19
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS62LV8006
1
Revision 2.1
Jan. 2004
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
READ CYCLE2 (1,3,4)
CE2
CE1
D OUT
t OH
t AA
t ACS2
t ACS1
t (5)
CLZ
t RC
READ CYCLE3 (1,4)
ADDRESS
OE
CE2
CE1
D OUT
t RC
t AA
t OE
t ACS2
t OLZ
t ACS1
t (5)
CLZ
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
BS62LV8006
t OH
t (5)
CHZ
t OH
t (5)
OHZ
t (1,5)
CHZ
R0201-BS62LV8006
5
Revision 2.1
Jan. 2004
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet BS62LV8006.PDF ] | |
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