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PDF BS62LV1029JIP55 Data sheet ( Hoja de datos )
| Número de pieza | BS62LV1029JIP55 | |
| Descripción | Very Low Power/Voltage CMOS SRAM 128K X 8 bit | |
| Fabricantes | Brilliance Semiconductor | |
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BSI Very Low Power/Voltage CMOS SRAM
128K X 8 bit
BS62LV1029
FEATURES
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade : 46mA (@55ns) operating current
I- grade : 47mA (@55ns) operating current
C-grade : 38mA (@70ns) operating current
I- grade : 39mA (@70ns) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
DESCRIPTION
The BS62LV1029 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.6uA at 5V/25oC and maximum access time of 55ns at 5V/85oC.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1029 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1029 is available in DICE form , JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP, 8mmx13.4
mm STSOP and 8mmx20mm TSOP.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
BS62LV1029SC
BS62LV1029TC
BS62LV1029STC
BS62LV1029PC
BS62LV1029JC
BS62LV1029DC
BS62LV1029SI
BS62LV1029TI
BS62LV1029STI
BS62LV1029PI
BS62LV1029JI
BS62LV1029DI
+0 O C to +70 O C
-40 O C to +85 O C
PIN CONFIGURATIONS
Vcc
RANGE
SPEED
(ns)
55ns :4.5~5.5V
70ns :4.5~5.5V
POWER DISSIPATION
STANDBY
Operating
(ICCSB1, Max)
Vcc=5.0V
(ICC, Max)
Vcc= 5.0V
55ns
70ns
4.5V ~ 5.5V
55/70
8.0uA
46mA 38mA
4.5V~ 5.5V
55/70
20uA
47mA 39mA
BLOCK DIAGRAM
PKG TYPE
SOP-32
TSOP-32
STSOP-32
PDIP-32
SOJ-32
DICE
SOP-32
TSOP-32
STSOP-32
PDIP-32
SOJ-32
DICE
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1 32
2 31
3 30
4 29
5 28
6 27
7 BS62LV1029SC 26
8 BS62LV1029SI 25
9 BS62LV1029PC 24
10
11
12
BS62LV1029PI
BS62LV1029JC
BS62LV1029JI
23
22
21
13 20
14 19
15 18
16 17
BS62LV1029TC
BS62LV1029STC
BS62LV1029TI
BS62LV1029STI
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
32
31 OE
30 A10
29 CE1
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 DQ3
23 GND
22 DQ2
21 DQ1
20 DQ0
19 A0
18 A1
17 A2
A3
A6
A7
A12
A14
A16
A15
A13
A8
A9
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE2
CE1
WE
OE
Vdd
Gnd
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 1024
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
1024
8 Column I/O
Write Driver
Sense Amp
8
128
Column Decoder
14
Address Input Buffer
A5 A4 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS62LV1029
1
Revision 1.1
Jan. 2004
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
t OH
t AA
t RC
READ CYCLE2 (1,3,4)
CE1
CE2
D OUT
t ACS1
t ACS2
t (5)
CLZ
READ CYCLE3 (1,4)
ADDRESS
OE
CE1
CE2
D OUT
t RC
t AA
t OE
t OLZ
t ACS1
t (5)
CLZ1
t ACS2
t (5)
CLZ2
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
BS62LV1029
t OH
t t(5)
CHZ1, CHZ2
t OH
t (5)
OHZ
t (1,5)
CHZ1
t (2,5)
CHZ2
R0201-BS62LV1029
5
Revision 1.1
Jan. 2004
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet BS62LV1029JIP55.PDF ] | |
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