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PDF CY7C1308DV25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1308DV25 | |
| Descripción | 9-Mbit 4-Word Burst SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1308DV25
9-Mbit 4-Word Burst SRAM with DDR-I
Architecture
Features
Functional Description
• 9-Mbit density (256 Kbit x 36)
• 167-MHz clock for high bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at
333 MHz @ 167 MHz)
• Two input clocks (K and K) for precise DDR
timing—SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL inputs and outputs
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG 1149.1 compatible test access port
Configuration
CY7C1308DV25 – 256K x 36
The CY7C1308DV25 is a 2.5V Synchronous Pipelined SRAM
equipped with DDR-I (Double Data Rate) architecture. The
DDR-I architecture consists of an SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Addresses for Read and Write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the
rising edges of both K and K. Read data is driven on the rising
edges of C and C if provided, or on the rising edge of K and K
if C/C are not provided. Every Read or Write operation is
associated with four words that burst sequentially into or out
of the device. The burst counter takes in the least two signif-
icant bits of the external address and bursts four 36-bit words.
Depth expansion is accomplished with Port Selects for each
port. Port Selects allow each port to operate independently.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks (C/C) are also provided for maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1308DV25)
A(1:0)
Burst
Logic
18 16
A(17:0)
Address
A(17:2) Register
LD
K
K
CLK
Gen.
Vref
R/W
BWS[3:0]
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
256K x 36 Array
Read Data Reg.
144 72
72
Output
Logic
Control
C
C
Reg.
Reg.
Reg.
36
36
36
CQ
CQ
DQ[35:0]
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05632 Rev. *A
Revised April 3, 2006
1 page  
Application Example[1]
DQ
A
SRAM#1
ZQ
CQ/CQ#
LD# R/W# C C# K K#
R = 250ohms
DQ
BUS
Addresses
MASTER Cycle Start#
(CPU
R/W#
or Return CLK
ASIC)
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
CY7C1308DV25
DQ
SRAM#2
ZQ
CQ/CQ#
A LD# R/W# C C# K K#
R = 250ohms
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K LD
Write Cycle:
Load address; wait one cycle; input
write data on 2 consecutive K and K
rising edges.
L-H L
Read Cycle:
Load address; wait one cycle; read data
on 2 consecutive C and C rising edges.
L-H
L
NOP: No Operation
L-H H
Standby: Clock Stopped
Stopped X
R/W DQ
L[8] D(A1)at
K(t+1)↑
DQ
D(A2) at
K(t+1)↑
DQ
D(A3) at
K(t+2) ↑
DQ
D(A4) at
K(t+2) ↑
H[9] Q(A1) at
C(t+1)↑
Q(A2) at
C(t+1) ↑
Q(A3) at
C(t+2)↑
Q(A4) at
C(t+2) ↑
X High-Z
High-Z
High-Z)
High-Z
X Previous State Previous State Previous State Previous State
Linear Burst Address Table
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X..X00
X..X01
X..X10
X..X11
X..X01
X..X10
X..X11
X..X00
X..X10
X..X11
X..X00
X..X01
X..X11
X..X00
X..X01
X..X10
Notes:
1. The above application shows 2 DDR-I being used.
2. X = “Don't Care“, H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A1” represents address location latched by the devices when transaction was initiated. A2, A3 and A4 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 and t+2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. This signal was HIGH on previous K clock rise. Initiating consecutive Write operations on consecutive K clock rises is not permitted. The device will ignore the
second Write request.
9. This signal was LOW on previous K clock rise. Initiating consecutive Read operations on consecutive K clock rises is not permitted.The device will ignore the
second Read request.
Document #: 38-05632 Rev. *A
Page 5 of 18
5 Page 
CY7C1308DV25
TAP AC Switching Characteristics Over the Operating Range[13, 14]
Parameter
Description
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TAP Timing and Test Conditions[14]
Min.
0
Max.
20
Unit
ns
ns
TDO
1.25V
50Ω
Z0 = 50Ω
CL = 20 pF
ALL INPUT PULSES
2.5V
1.25V
0V
(a) GND
Test Clock
TCK
Test Mode Select
TMS
Test Data-In
TDI
tTH tTL
tTMSS
tTCYC
tTMSH
tTDIS
tTDIH
Test Data-Out
TDO
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
tTDOX
tTDOV
Value
CY7C1308DV25
000
01011111011100110
00000110100
1
Description
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Document #: 38-05632 Rev. *A
Page 11 of 18
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C1308DV25.PDF ] | |
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