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ON Semiconductor |
MC10E158, MC100E158
5 V ECL 5‐Bit 2:1 Multiplexer
Description
The MC10E/100E158 contains five 2:1 multiplexers with
differential outputs. The output data are controlled by the Select input
(SEL).
The 100 Series contains temperature compensation.
Features
• 600 ps Max. D to Output
• 800 ps Max. SEL to Output
• Differential Outputs
• One VCCO Pin Per Output Pair
• PECL Mode Operating Range:
♦ VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range:
♦ VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input 50 kW Pulldown Resistors
• ESD Protection:
♦ Human Body Model; > 2 kV
♦ Machine Model; > 200 V
• Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level: 3 (Pb-Free)
♦ For Additional Information, see Application Note AND8003/D
• Flammability Rating:
♦ UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
• Transistor Count = 126 devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
PLCC−28
FN SUFFIX
CASE 776−02
MARKING DIAGRAM*
1
MCxxxE158FNG
AWLYYWW
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
MC10E158FNG
MC10E158FNR2G
MC100E158FNG
Package
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
Shipping†
37 Units/Tube
500/Tape & Reel
37 Units/Tube
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 10
1
Publication Order Number:
MC10E158/D
MC10E158, MC100E158
D4a D3b D3a VCCO Q4 Q4 VCCO
25 24 23 22 21 20 19
D4b 26
18
D2a 27
D2b 28
VEE
1
SEL 2
Pinout: 28-Lead PLCC
(Top View)
17
16
15
14
D0a 3
D0b 4
13
12
Q3
Q3
VCC
Q2
Q2
VCCO
Q1
5 6 7 8 9 10 11
D1a D1b VCCO Q0 Q0 VCCO Q1
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. 28-Lead Pinout
D0a MUX Q0
D0b SEL Q0
D1a MUX Q1
D1b SEL Q1
D2a MUX Q2
D2b SEL Q2
D3a MUX Q3
D3b SEL Q3
D4a MUX Q4
D4b SEL Q4
SEL
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
PIN FUNCTION
D0a − D4a
D0b − D4b
Q0 − Q4
Q0 − Q4
SEL
ECL Input Data a
ECL Input Data b
ECL True Outputs
ECL Inverted Outputs
ECL Select Input
VCC, VCCO
VEE
Table 2. Logic Diagram
Positive Supply
Negative Supply
SEL Data
Ha
Lb
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