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PDF SI7748DP Data sheet ( Hoja de datos )
| Número de pieza | SI7748DP | |
| Descripción | N-Channel 30-V (D-S) MOSFET | |
| Fabricantes | Vishay Siliconix | |
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New Product
Si7748DP
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET with Schottky Diode
PRODUCT SUMMARY
VDS (V)
30
RDS(on) (Ω)
0.0048 at VGS = 10 V
0.0066 at VGS = 4.5 V
ID (A)a
50
50
Qg (Typ.)
27.8 nC
PowerPAK® SO-8
6.15 mm
D
8D
7
D
6
D
5
S
1S
5.15 mm
2
S
3
G
4
Bottom View
Ordering Information: Si7748DP-T1-GE3 (Lead (Pb)-free and Halogen-free)
FEATURES
• Halogen-free
• SkyFET™ Monolithic TrenchFET®
Power MOSFET and Schottky Diode
• 100 % Rg Tested
• 100 % UIS Tested
APPLICATIONS
• Notebook
- Vcore Low-Side
D
RoHS
COMPLIANT
G
N-Channel MOSFET
S
Schottky Diode
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
Drain-Source Voltage
Gate-Source Voltage
VDS
VGS
Continuous Drain Current (TJ = 150 °C)
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
ID
Pulsed Drain Current
Continuous Source-Drain Diode Current
TC = 25 °C
TA = 25 °C
IDM
IS
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
L = 0.1 mH
IAS
EAS
TC = 25 °C
Maximum Power Dissipation
TC = 70 °C
TA = 25 °C
PD
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d, e
TA = 70 °C
TJ, Tstg
Limit
30
± 20
50a
50a
23.5b, c
18.6b, c
80
50a
4.3b, c
30
45
56
31
4.8b, c
3b, c
- 55 to 150
260
Unit
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambientb, f
Maximum Junction-to-Case (Drain)
t ≤ 10 s
Steady State
RthJA
RthJC
21
1.7
26
°C/W
2.2
Notes:
a. Package limited.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See Solder Profile (http://www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions is 68 °C/W.
Document Number: 68785
S-81714-Rev. A, 04-Aug-08
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TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
75
Si7748DP
Vishay Siliconix
60
Package Limited
45
30
15
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Current Derating*
70 2.25
56 1.80
42 1.35
28 0.90
14 0.45
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Power, Junction-to-Case
0.00
0
25 50 75 100 125
TA - Ambient Temperature (°C)
Power, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 68785
S-81714-Rev. A, 04-Aug-08
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AN821
Vishay Siliconix
SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 7).
On-Resistance vs. Junction Temperature
1.8
1.6
VGS = 10 V
ID = 23 A
1.4
1.2
1.0
Suppose each device is dissipating 2.7 W. Using the
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die tem-
perature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This
is a 2 °C rise above the board temperature for the Pow-
erPAK and a 43 °C rise for the standard SO-8. Referring
to Figure 7, a 2 °C difference has minimal effect on
rDS(on) whereas a 43C difference has a significant effect
on rDS(on).
Minimizing the thermal rise above the board tempera-
ture by using PowerPAK has not only eased the thermal
design but it has allowed the device to run cooler, keep
rDS(on) low, and permits the device to handle more cur-
rent than the same MOSFET die in the standard SO-8
package.
0.8
0.6
- 50 - 25
0
25 50 75 100 125 150
TJ - Junction Temperature (°C)
Figure 7. MOSFET rDS(on) vs. Temperature
A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises
the junction temperature of the device above that of the
PC board to which it is mounted, causing increased
power dissipation in the device. A major source of this
problem lies in the large values of the junction-to-foot
thermal resistance of the SO-8 package.
PowerPAK SO-8 minimizes the junction-to-board ther-
mal resistance to where the MOSFET die temperature is
very close to the temperature of the PC board. Consider
two devices mounted on a PC board heated to 105 °C
by other components on the board (Figure 8).
PowerPAK SO-8
107 °C
Standard SO-8
148 °C
CONCLUSIONS
PowerPAK SO-8 has been shown to have the same
thermal performance as the DPAK package while hav-
ing the same footprint as the standard SO-8 package.
The PowerPAK SO-8 can hold larger die approximately
equal in size to the maximum that the DPAK can accom-
modate implying no sacrifice in performance because of
package limitations.
Recommended PowerPAK SO-8 land patterns are pro-
vided to aid in PC board layout for designs using this
new package.
Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and typical
thermal performance in a SO-8 environment, plus infor-
mation on the optimum thermal performance obtainable
including spreading copper. This further emphasized the
DPAK equivalency.
PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.
0.8 °C/W
PC Board at 105 °C
16 C/W
Figure 8. Temperature of Devices on a PC Board
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Document Number 71622
28-Feb-06
Datasheet pdf - http://www.DataSheet4U.net/
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