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PDF LTC4441 Data sheet ( Hoja de datos )
| Número de pieza | LTC4441 | |
| Descripción | N-Channel MOSFET Gate Driver | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC4441 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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FEATURES
■ 6A Peak Output Current
■ Wide VIN Supply Range: 5V to 25V
■ Adjustable Gate Drive Voltage: 5V to 8V
■ Logic Input can be Driven Below Ground
■ 30ns Propagation Delay
■ Supply Independent CMOS/TTL Input Thresholds
■ Undervoltage Lockout
■ Low Shutdown Current: <12µA
■ Overtemperature Protection
■ Adjustable Blanking Time for MOSFET’s
Current Sense Signal (LTC4441)
■ Available in SO-8 and 10-Lead MSOP
(Exposed Pad) Packages
U
APPLICATIO S
■ Power Supplies
■ Motor/Relay Control
■ Line Drivers
■ Charge Pumps
LTC444w1w/wL.DTatCaSh4ee4t4U4.c1om-1
N-Channel MOSFET
Gate Driver
DESCRIPTIO
The LTC®4441/LTC4441-1 is an N-channel MOSFET gate
driver that can supply up to 6A of peak output current. The
chip is designed to operate with a supply voltage of up to
25V and has an adjustable linear regulator for the gate
drive. The gate drive voltage can be programmed between
5V and 8V.
The LTC4441/LTC4441-1 features a logic threshold driver
input. This input can be driven below ground or above the
driver supply. A dual function control input is provided to
disable the driver or to force the chip into shutdown mode
with <12µA of supply current. Undervoltage lockout and
overtemperature protection circuits will disable the driver
output when activated. The LTC4441 also comes with an
open-drain output that provides adjustable leading edge
blanking to prevent ringing when sensing the source
current of the power MOSFETs.
The LTC4441 is available in a thermally enhanced 10-lead
MSOP package. The LTC4441-1 is the SO-8 version with-
out the blanking function.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents
including 6677210.
TYPICAL APPLICATIO
VIN
6V TO 24V
R5
SHUTDOWN Q2 R6
LTC3803
SWITCHING
CONTROLLER
GATE
SENSE+
R1
330k
R2
86.6k
VIN
FB DRVCC
SGND
OUT
LTC4441
EN/SHDN
R7
RBLANK PGND
IN BLANK
GND
FB
L1 D1
10µH 20A MBR10100
+ 22µF
25V
X7R
+
COUT
CVCC
10µF
X5R
Si7370
×2
R3
5mΩ
VOUT
52V
2A
R4
100Ω
R8
511k
R9
8.06k
4441 TA01
RISE/FALL Time vs CLOAD
200
TA = 25°C
180 DRVCC = 5V
160
140
120
100
RISE TIME
80
60
40
FALL TIME
20
0
0 5 10 15 20 25 30 35 40 45 50
CLOAD (nF)
4441 TA01b
44411f
1
1 page  
TYPICAL PERFOR A CE CHARACTERISTICS
LTC444w1w/wL.DTatCaSh4ee4t4U4.c1om-1
tPLH, tPHL vs CLOAD
100
TA = 25°C
90 DRVCC = 5V
80
tPLH
70
60
50
40 tPHL
30
20
10
0
0 5 10 15 20 25 30 35 40 45 50
CLOAD (nF)
4441 G13
RISE/FALL Time vs DRVCC
30
TA = 25°C
CLOAD = 4.7nF
25
20
15 RISE TIME
10 FALL TIME
5
0
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0
DRVCC (V)
4441 G14
RISE/FALL Time vs Temperature
30
DRVCC = 5V
CLOAD = 4.7nF
25
20
RISE TIME
15
10
FALL TIME
5
0
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
4441 G15
RISE/FALL Time vs CLOAD
200
TA = 25°C
180 DRVCC = 5V
160
140
120
100
RISE TIME
80
60
40
FALL TIME
20
0
0 5 10 15 20 25 30 35 40 45 50
CLOAD (nF)
4441 G16
Blanking Time vs RBLANK
500
TA = 25°C
450 DRVCC = 5V
LTC4441
400
350
300
250
200
150
100
50
0
0 100 200 300 400 500 600 700
RBLANK (kΩ)
4441 G17
Blanking Time vs Temperature
250
VIN = 7.5V
240 DRVCC = 5V
LTC4441
230
220
210
200
190
180
170
160
150
–50 –25
0 25 50 75 100 125
TEMPERATURE (°C)
4441 G18
VIN Operating Supply Current vs
Temperature
500
EN = 5V
450 IN = 0V
400
350
300 VIN = 25V
250
VIN = 7.5V
200
150
100
50
0
–50 –25
0 25 50 75 100 125
TEMPERATURE (°C)
4441 G19
VIN Standby Supply Current vs
Temperature
15
EN = 0V
14 IN = 0V
13
12 VIN = 25V
11
10
9
8
7
6 VIN = 7.5V
5
4
3
–50 –25
0 25 50 75 100 125
TEMPERATURE (°C)
4441 G20
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LTC444w1w/wL.DTatCaSh4ee4t4U4.c1om-1
APPLICATIO S I FOR ATIO
check with power MOSFET manufacturers for their
innovations on low QG, low RDS(ON) devices. Power
MOSFET manufacturing technologies are continually im-
proving, with newer and better performing devices being
introduced.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC4441/LTC4441-1:
A. Mount the bypass capacitors as close as possible
between the DRVCC and PGND pins and between the VIN
and SGND pins. The PCB trace loop areas should be
tightened as much as possible to reduce inductance.
B. Use a low inductance, low impedance ground plane to
reduce any ground drop. Remember that the LTC4441/
LTC4441-1 switches 6A peak current and any significant
ground drop will degrade signal integrity.
C. Keep the PCB ground trace between the LTC4441/
LTC4441-1 ground pins (PGND and SGND) and the exter-
nal current sense resistor as short and wide as possible.
D. Plan the ground routing carefully. Know where the large
load switching current paths are. Maintain separate ground
return paths for the input pin and output pin to avoid
sharing small-signal ground with large load ground re-
turn. Terminate these two ground traces only at the GND
pin of the driver (STAR network).
E. Keep the copper trace between the driver output pin and
the load short and wide.
F. Place the small-signal components away from the high
frequency switching nodes. These components include
the resistive networks connected to the FB, RBLANK and
EN/SHDN pins.
PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 ± 0.102
1 (.081 ± .004)
1.83 ± 0.102
(.072 ± .004)
5.23
(.206)
MIN
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
0.254
(.010)
GAUGE PLANE
DETAIL “A”
0° – 6° TYP
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
RECOMMENDED SOLDER PAD LAYOUT
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE 0.17 – 0.27
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
(.007 – .011)
TYP
0.50
(.0197)
BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
0.127 ± 0.076
(.005 ± .003)
10
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
10 9 8 7 6
0.497 ± 0.076
(.0196 ± .003)
REF
4.90 ± 0.152
(.193 ± .006)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
12345
MSOP (MSE) 0603
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LTC4441.PDF ] | |
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