ADSP-2196 판매점 - DSP Microcomputer

ADSP-2196 반도체 회로 부품 판매점

DSP Microcomputer

Analog Devices

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aPrelitamSinheaeryt4TUe.ccohmnical Data DSP MAicDrSoPc-o2m1p9u6terADSP-219x DSP CORE FEATURES

6.25 ns Instruction Cycle Time (Internal), for up to

a160 MIPS Sustained Performance

.DADSP-218x Family Code Compatible with the Same

wEasy -to-Use Algebraic Syntax

Single-Cycle Instruction Execution

w Up to 16M words of Addressable Memory Space with

w 24 Bits of Addressing Width

mDual Purpose Program Memory for Both Instruction and

Data Storage

oFully Transparent Instruction Cache Allows Dual

Operand Fetches in Every Instruction Cycle

.cUnified Memory Space Permits Flexible Address

Generation, Using Two Independent DAG Units

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units with Dual 40-bit

Accumulators

Single-Cycle Context Switch between Two Sets of

Computational and DAG Registers

Parallel Execution of Computation and Memory

Instructions

Pipelined Architecture Supports Efficient Code

Execution at Speeds up to 160 MIPS

Nonparallel Computational Instructions

Powerful Program Sequencer Provides Zero-Overhead

Looping and Conditional Instruction Execution

Architectural Enhancements for Compiled C

Code Efficiency

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FUNCTIONAL BLOCK DIAGRAM

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w.DThis information applies to a product under development. Its characteristics

and specifications are subject to change without notice. Analog Devices

wassumes no obligation regarding future manufacturing unless otherwise

wagreed to in writing.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:781/329-4700 World Wide Web Site: http://www.analog.com

Fax:781/326-8703

©Analog Devices,Inc., 2001

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ADSP-2196

For current information contact Analog Devices at 800/262-5643

September 2001

ADSP-2196 DSP FEATURES

16K Words of On-Chip RAM, Configured as 8K Words

On-Chip 24-bit RAM and 8K Words On-Chip 16-bit RAM

16K Words of On-Chip 24-bit ROM

Architecture Enhancements beyond ADSP-218x Family

are Supported with Instruction Set Extensions for

Added Registers, Ports, and Peripherals

Flexible Power Management with Selectable

Power-Down and Idle Modes

Programmable PLL Supports 1؋ to 32؋ Frequency

Multiplication, Enabling Full-Speed Operation from

Low-Speed Input Clocks

2.5 V Internal Operation Supports 3.3 V Compliant I/O

Three Full-Duplex Multichannel Serial Ports, Each

Supporting H.100 Standard with A-Law and ␮-Law

Companding in Hardware

Two SPI-Compatible Ports with DMA Capability

One UART Port with DMA Capability

16 General-Purpose I/O Pins (Eight Dedicated/Eight

Programmable from the External Memory Interface)

with Integrated Interrupt Support

Three Programmable 32-Bit Interval Timers with

Pulsewidth Counter, PWM Generation, and Externally

Clocked Timer Capabilities

Up to 11 DMA Channels can be Active at any Given Time

Host Port With DMA Capability for Efficient, Glueless Host

Interface (16-Bit Transfers)

External Memory Interface Features Include:

Direct Access from the DSP to External Memory for

Data and Instructions.

Support for DMA Block Transfers to/from

External Memory.

Separate Peripheral Memory Space with Parallel

Support for 224K External 16-Bit Registers.

Four General-Purpose Memory Select Signals that

Provide Access to Separate Banks of External

Memory. Bank Boundaries and Size Are User-

Programmable.

Programmable Waitstate Logic with ACK Signal and

Separate Read and Write Wait Counts. Wait Mode

Completion Supports All Combinations of ACK

and/or Wait Count.

I/O Clock Rate Can Be Set to the Peripheral Clock Rate

Divided by 1, 2, 4, 16, or 32 to Allow Interface to Slow

Memory Devices.

Address Translation and Data Word Packing is Provided

to Support an 8- or 16-Bit External Data Bus.

Programmable Read and Write Strobe Polarity.

Separate Configuration Registers for the Four

General-Purpose, Peripheral, and Boot

Memory Spaces.

Bus Request and Grant Signals Support the Use of the

External Bus by an External Device.

Boot Methods Include Booting Through External Memory

Interface, SPI Ports, UART Port, or Host Interface

IEEE JTAG Standard 1149.1 Test Access Port Supports

On-Chip Emulation and System Debugging

144-Lead LQFP Package (20 ؋ 20 ؋ 1.4 mm) and 144-Lead

Mini-BGA Package (10 ؋ 10 ؋ 1.25 mm)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

REV. PrA

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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제조업체: Analog Devices

( analogs )

ADSP-2196 microcomputer

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ADSP-2196 반도체 회로 부품 판매점

DSP Microcomputer

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